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w WM8903 ultra low power codec for portable audio applications wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/ enews production data, june 2012, rev 4.5 copyright ? 2012 wolfson microelectronics plc description the WM8903 is a high performance ultra-low power stereo codec optimised for portable audio applications. the device features stereo ground-referenced headphone amplifiers using the wolfson ?class w? amplifier techniques - incorporating an innovative dual-mode charge pump architecture - to optimise e fficiency and power consumption during playback. the ground-referenced outputs eliminate headphone coupling capacitors. both headphone and line outputs include common mode feedback paths to reject ground noise. control sequences for audio path setup can be pre-loaded and executed by an integrated sequencer to reduce software driver development and eliminate pops and clicks via wolfson?s silentswitch? technology. the analogue input stage can be configured for single ended or differential inputs. up to 3 stereo microphone or line inputs may be connected. the input impedance is constant with pga gain setting. a stereo digital microphone interf ace is provided, which can also be mixed with the mic/li ne signals at the output mixers. a dynamic range controller provides compression and level control to support a wide range of portable recording applications. anti-clip and quick release features offer good performance in the presence of loud impulsive noises. common audio sampling frequencies are supported from a range of external clocks, either directly or generated via the frequency locked loop (fll). the WM8903 can operate directly from a single 1.8v switched supply. for optimal pow er consumption, the digital core can be operated from a 1.0v supply. features ? 4.5mw power consumption for dac to headphone playback ? dac snr 96db typical, thd -86db typical ? adc snr 92db typical, thd -80db typical ? control sequencer for pop mi nimised start-up and shut- down ? single register write for default start-up sequence ? integrated fll provides all necessary clocks - self-clocking modes allow processor to sleep - all standard sample rates from 8khz to 96khz ? stereo digital microphone input ? 3 single ended inputs per stereo channel ? 1 fully differential mic / line input per stereo channel ? digital dynamic range controller (compressor / limiter) ? digital sidetone mixing ? ground-referenced headphone driver ? ground-referenced line outputs ? stereo differential line driver for direct interface to wm9001 speaker driver ? 40-pin qfn package (5x5mm) applications ? portable multimedia players ? multimedia handsets ? handheld gaming
WM8903 production data w pd, rev 4.5, june 2012 2 block diagram control interface WM8903 dcvdd dbvdd dgnd hpoutl_vol hpoutl audio interface dynamic range control volume digital mono mix digital side tone digital filters volume digital mono mix fll / clock circuitry linegnd (headphone / line output) hpgnd vpos cpgnd charge pump cfb1 cpvdd vneg cfb2 in1l in2l in3l pga + mic boost ron spkr_vol rop lon spkr_vol lop micbias + - pga + mic boost + - hpoutr lineoutl lineoutr m u x vmid reference (headphone / line output) (differential line output) dac adc adc dac in1r in2r in3r m u x left spkr mixer left mixer right mixer right spkr mixer stereo digital mic interface dmic_lr / gpio1 dmic_dat / gpio2 hpoutr_vol lineoutl_vol lineoutr_vol
production data WM8903 w pd, rev 4.5, june 2012 3 table of contents descript ion ....................................................................................................... 1 ? featur es ............................................................................................................ 1 ? applications ..................................................................................................... 1 ? block diag ram ................................................................................................ 2 ? table of co ntents ......................................................................................... 3 ? pin config uration .......................................................................................... 6 ? ordering info rmation .................................................................................. 6 ? pin descri ption ................................................................................................ 7 ? absolute maximu m ratings ........................................................................ 8 ? recommended operatin g condit ions ..................................................... 8 ? electrical charact eristics ..................................................................... 9 ? terminology ............................................................................................................... 9 ? common test co nditions ....................................................................................... 9 ? input signal path .................................................................................................... 10 ? output signal path ................................................................................................ 12 ? bypass path .............................................................................................................. 14 ? charge pu mp ............................................................................................................. 15 ? fll ........................................................................................................................... ...... 15 ? other parameters ................................................................................................. 15 ? power consum ption .................................................................................... 17 ? common test co nditions ..................................................................................... 17 ? power consumption measurements ............................................................... 17 ? signal timing re quiremen ts .................................................................... 19 ? common test co nditions ..................................................................................... 19 ? master clock ........................................................................................................... 19 ? audio interface timing ......................................................................................... 20 ? master mode ................................................................................................................... ........................................... 20 ? slave mode ............................................................................................................................... ................................... 21 ? tdm mode ...................................................................................................................... ............................................... 22 ? control interface timing ................................................................................... 23 ? digital filter charact eristics .............................................................. 24 ? dac filter responses ........................................................................................... 25 ? adc filter responses ........................................................................................... 26 ? adc high pass filter responses ....................................................................... 27 ? de-emphasis filte r responses .......................................................................... 28 ? device des cription ...................................................................................... 29 ? introduction ............................................................................................................ 29 ? analogue input si gnal path ............................................................................... 30 ? input pga enable .............................................................................................................. ........................................ 31 ? input pga conf iguration ....................................................................................................... ............................... 31 ? single-ended input ............................................................................................................ ...................................... 33 ? differential line input ............................................................................................................................... ............ 33 ? differential microphone input ................................................................................................. ......................... 34 ? input pga gain control ........................................................................................................ ................................. 34 ? input pga common mode amplifier ............................................................................................... ..................... 36 ? electret condenser mi crophone interface .............................................. 37 ? micbias current detect ........................................................................................................ ................................ 37 ? micbias current detect filtering .............................................................................................. ...................... 38 ?
WM8903 production data w pd, rev 4.5, june 2012 4 microphone hook switch detection .............................................................................................. .................. 39 ? digital microphon e interface .......................................................................... 40 ? analogue-to-digital converter (adc) ............................................................ 42 ? adc digital volume control .................................................................................................... ............................ 42 ? high-pass filter (hpf) ........................................................................................................ ..................................... 45 ? adc oversampling ratio (osr) .................................................................................................. .......................... 46 ? dynamic range co ntrol (drc) ........................................................................... 46 ? compression/limiting capabilities ............................................................................................. ....................... 46 ? gain limits ............................................................................................................................... ..................................... 48 ? dynamic characteristics ....................................................................................................... .............................. 49 ? anti-clip control ............................................................................................................. ........................................ 50 ? quick release control ......................................................................................................... ................................ 50 ? gain smoothing ................................................................................................................ ......................................... 51 ? initialisation ................................................................................................................ .............................................. 52 ? digital mixing ............................................................................................................ 53 ? digital mixing paths .......................................................................................................... ...................................... 53 ? dac interface volume boost .................................................................................................... .......................... 54 ? digital sidetone ............................................................................................................................... ......................... 55 ? digital-to-analogue converter (dac) ............................................................ 56 ? dac digital volume control .................................................................................................... ............................ 57 ? dac soft mute and soft un-mute ................................................................................................ ....................... 59 ? dac mono mix .................................................................................................................. ............................................ 60 ? dac de-emphasis ............................................................................................................................... ......................... 60 ? dac sloping stopband filter ................................................................................................... ........................... 61 ? dac bias control ............................................................................................................................... ....................... 61 ? dac oversampling ratio (osr) .................................................................................................. .......................... 62 ? output signal path ................................................................................................ 63 ? output signal paths enable .................................................................................................... ............................ 64 ? headphone / line output signal paths enable ................................................................................... .......... 65 ? output pga bias control ....................................................................................................... ............................... 68 ? output drivers bias control ................................................................................................... .......................... 68 ? output mixer control .......................................................................................................... ................................. 69 ? output volume control ......................................................................................................... .............................. 71 ? analogue outputs ................................................................................................. 75 ? headphone outputs ? hpoutl and hpoutr ......................................................................................... ............ 75 ? line outputs ? lineoutl and lineoutr .......................................................................................... ................... 75 ? differential line outputs ? lon/lop and ron/rop ............................................................................... ....... 75 ? external components for ground-referenced outputs ...................................................................... 76 ? reference voltages a nd master bias ........................................................... 77 ? pop suppression control .................................................................................. 79 ? disabled input / output control ............................................................................................... ........................ 79 ? differential line output discharge control .................................................................................... .......... 79 ? charge pu mp ............................................................................................................. 80 ? dc servo ..................................................................................................................... 81 ? digital audio interface ........................................................................................ 84 ? master and slave mode operation ............................................................................................... .................... 84 ? operation with tdm ............................................................................................................ ..................................... 85 ? bclk frequency ................................................................................................................ ........................................ 86 ? audio data formats (normal mode) .............................................................................................. .................... 86 ? audio data formats (tdm mode) ................................................................................................. ........................ 88 ? digital audio inte rface control ..................................................................... 90 ? bclk and lrclk control ........................................................................................................ ................................ 91 ? companding .................................................................................................................... ............................................ 93 ? loopback ...................................................................................................................... ............................................... 94 ?
production data WM8903 w pd, rev 4.5, june 2012 5 clocking and sample rates ................................................................................ 95 ? clk_sys control ............................................................................................................... ....................................... 97 ? control interface clocking .................................................................................................... .......................... 98 ? automatic clocking configuration .............................................................................................. ................... 98 ? usb clocking mode ............................................................................................................. ................................... 100 ? adc / dac operation at 88.2k / 96k ............................................................................................ ......................... 100 ? digital microphone (dmic) operation ........................................................................................... ................. 101 ? frequency locked loop (fll) ........................................................................... 101 ? free-running fll clock ........................................................................................................ ............................... 105 ? gpio outputs from fll ......................................................................................................... ................................ 105 ? example fll calculation ............................................................................................................................... ...... 105 ? example fll settings .......................................................................................................... .................................. 106 ? general purpose input/ output (gpio) .......................................................... 107 ? interrupts .............................................................................................................. 112 ? control interface ............................................................................................... 115 ? control write sequencer ................................................................................ 118 ? initiating a sequence ............................................................................................................................... ............. 118 ? programming a sequence ........................................................................................................ .......................... 119 ? default sequences ............................................................................................................. .................................. 122 ? start-up sequence ............................................................................................................. ................................... 122 ? shutdown sequence ............................................................................................................................... .............. 125 ? power-on reset .................................................................................................... 127 ? quick start-up a nd shutdown ........................................................................ 129 ? quick start-up (default sequence) ............................................................................................. ................... 129 ? quick shutdown (default sequence) ............................................................................................. ............... 129 ? software reset a nd chip id ............................................................................. 130 ? register map ................................................................................................ 131 ? register bits by address .................................................................................. 134 ? applications in formation ...................................................................... 172 ? recommended external components .......................................................... 172 ? mic detection sequence us ing micbias current ..................................... 174 ? package dime nsions .................................................................................. 176 ? important no tice ....................................................................................... 177 ? address .................................................................................................................... 17 7 ? revision hi story ......................................................................................... 178 ?
WM8903 production data w pd, rev 4.5, june 2012 6 pin configuration ordering information device temperature range package moisture sensitivity level peak soldering temperature WM8903clgefk -40c to +85c 40-lead qfn (5x5x0.55mm, lead-free) msl1 260c WM8903clgefk/r -40c to +85c 40-lead qfn (5x5x0.55mm, lead-free, tape and reel) msl1 260c note: tube quantity = 95 reel quantity = 3,500
production data WM8903 w pd, rev 4.5, june 2012 7 pin description pin name type description 1 dgnd supply digital ground (return path for dcvdd and dbvdd) 2 mclk digital input master clock for codec 3 gpio2/ dmic_dat digital input/output gpio2 / digital microphone data input 4 gpio1/ dmic_lr digital input/output gpio1 / digital microphone clock output 5 interrupt digital output interrupt output / gpio4 6 bclk digital input/output audio interface bit clock / gpio5 7 dacdat digital input dac digital audio data 8 lrc digital input/output audio interface left / right clock (common for adc and dac) 9 adcdat digital output adc digital audio data 10 cpvdd supply charge pump power supply 11 cfb1 analogue output charge pump flyback capacitor pin 12 cpgnd supply charge pump ground 13 cfb2 analogue output charge pump flyback capacitor pin 14 vpos analogue output charge pump positive supply decoupling (powers hpoutl/r, lineoutl/r) 15 vneg analogue output charge pump negative supply dec oupling (powers hpoutl/r, lineoutl/r) 16 hpoutr analogue output right headphone output (line or headphone output) 17 hpgnd analogue input headphone ground 18 hpoutl analogue output left headphone output (line or headphone output) 19 lineoutr analogue output right line output 1 (line output) 20 linegnd analogue input line-out ground 21 lineoutl analogue output left line output 1 (line output) 22 lop analogue output left differential output positive side 23 lon analogue output left differential output negative side 24 avdd supply analogue power supply (powers analogue i nputs, reference, adc, dac, lop, lon, rop, ron) 25 vmid analogue output midrail voltage decoupling capacitor 26 agnd supply analogue power return 27 ron analogue output right differential output negative side 28 rop analogue output right differential output positive side 29 micbias analogue output microphone bias 30 in3r analogue input right channel input 3 31 in2r analogue input right channel input 2 32 in1r analogue input right channel input 1 33 in3l analogue input left channel input 3 34 in2l analogue input left channel input 2 35 in1l analogue input left channel input 1 36 sdin digital input/output control interface data input / 2-wire acknowledge output 37 sclk digital input control interface clock input 38 gpio3 /addr digital input/output gpio3 / control interface address selection 39 dcvdd supply digital core supply 40 dbvdd supply digital buffer supply (powers audi o interface and control interface)
WM8903 production data w pd, rev 4.5, june 2012 8 absolute maximum ratings absolute maximum ratings are stress ratings only. pe rmanent damage to the device ma y be caused by continuously operating at or beyond these limits. device functional operat ing limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static vo ltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std- 020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 ? c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specif ied in ordering information. condition min max avdd, dcvdd -0.3v +2.5v dbvdd, -0.3v +4.5v cpvdd -0.3v +2.2v hpoutl, hpoutr, lineoutl, lineoutr (cpvdd + 0.3v) * -1 cpvdd + 0.3 voltage range digital inputs dgnd -0.3v dbvdd +0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v temperature range, t a -40 ? c +85 ? c storage temperature after soldering -65 ? c +150 ? c notes 1. analogue and digital grounds must always be within 0.3v of each other. 2. all digital and analogue supplies are completely independent fr om each other; there is no restriction on power supply sequencing. 3. hpoutl, hpoutr, lineoutl, lineoutr are outputs, and should not normally become connected to dc levels. however, if the limits above are exceeded, then damage to the WM8903 may occur. recommended operating conditions parameter symbol min typ max unit digital supply range (core) dcvdd 0.95 1.2 1.89 v digital supply range (buffer) dbvdd 1.42 1.8 3.6 v analogue supplies range avdd 1.71 1.8 2.0 v charge pump supply range cpvdd 1.71 1.8 2.0 v ground dgnd, agnd, cpgnd 0 v operating temperature (ambient) t a -40 +25 +85 ? c
production data WM8903 w pd, rev 4.5, june 2012 9 electrical characteristics terminology 1. signal-to-noise ratio (db) ? snr is the difference in level between a full scale output signal and the device output noise with no signal applied, measured over a bandwidth of 20h z to 20khz. this ratio is al so called idle channel noise. (no auto-zero or automute function is employed). 2. total harmonic distortion (db) ? thd is the difference in level between a 1khz full scale sinewave output signal and the first seven harmonics of the output signal. the amp litude of the fundamental frequency of the output signal is compared to the rms value of the next se ven harmonics and expressed as a ratio. 3. total harmonic distortion + noise (db) ? thd+n is the di fference in level between a 1khz full scale sine wave output signal and all noise and distortion products in the audio band. the amplitude of the fundamental reference frequency of the output signal is compared to the rms value of all other noise and distortion products and expressed as a ratio. 4. channel separation (db) ? is a measure of the coupli ng between left and right channels. a full scale signal is applied to the left channel only, the right channel amplitude is measured. then a full scale signal is applied to the right channel only and the left channel amplitude is measured. the wo rst case channel separati on is quoted as a ratio. 5. channel level matching (db) ? m easures the difference in gain betw een the left and the right channels. 6. power supply rejection ratio (db) ? psrr is a meas ure of ripple attenuation between the power supply pin and an output path. with the signal path idle, a small signal sine wa ve is summed onto the power supply rail, the amplitude of the sine wave is measured at the output port and expressed as a ratio. 7. all performance measurements carried out with 20khz aes17 low pass filter for distortion measurements, and an a-weighted filter for noise measurement. failure to use such a filter will result in higher thd and lower snr and dynamic range readings than are found in the electrical characteristics. t he low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. common test conditions unless otherwise stated, the following test conditions apply throughout the following sections: ? dcvdd = 1.2v ? dbvdd = 1.8v ? avdd = cpvdd =1.8v ? ambient temperature = +25c ? audio signal: 1khz sine wave, sampled at 48khz with 24-bit data resolution additional, specific test c onditions are given within t he relevant sections below.
WM8903 production data w pd, rev 4.5, june 2012 10 input signal path single-ended stereo line record - in1l+in1r pins to adc output test conditions: l_mode = r_mode = 00b (single ended) lin_vol = rin_vol = 00000b (-1.55db) total signal path gain = 4.45db, incorporating 6db single-ended to differential conversion gain parameter symbol test conditions min typ max unit full scale input signal level (for adc 0dbfs). 0.570 -4.88 1.61 0.600 -4.45 1.70 0.630 -4.01 1.78 vrms dbv vpk-pk input resistance r in 10 12 k ? input capacitance c in 10 pf dc offset at adc output with adc_hpf_ena=0 11864 lsbs (24-bit) 47 lsbs (16-bit) signal to noise ratio snr a-weighted 85 91 dbfs total harmonic distortion thd -5.45dbv input -78 -68 dbfs total harmonic distortion + noise thd+n -5.45dbv input -76 -66 dbfs channel separation 1khz signal, -5.45dbv 85 db 10khz signal, -5.45dbv 80 channel level matching 1khz signal, -5.45dbv +/-1 db power supply rejection ratio psrr 1khz, 100mvpk-pk 60 db 20khz, 100mv pk-pk 40 differential stereo line record - in2l+in3l / in2r+in3r pins to adc output test conditions: l_mode = r_mode = 01b (differential line) lin_vol = rin_vol = 01111b (+4.2db) total signal path gain = +4.20db parameter symbol test conditions min typ max unit differential line input full scale signal level in2l-in3l or in2r- in3l (for adc 0dbfs output) 0.586 -4.64 1.657 0.617 -4.20 1.745 0.648 -3.77 1.833 vrms dbv vpk-pk input resistance r in 10 12 k ? input capacitance c in 10 pf dc offset at adc output with adc_hpf_ena=0 11864 lsbs (24-bit) 47 lsbs (16-bit) signal to noise ratio snr a-weighted 85 92 dbfs total harmonic distortion thd -5.2dbv input -80 -66 dbfs total harmonic distortion + noise thd+n -5.2dbv input -78 -64 dbfs common mode rejection ratio cmrr 1khz, 100mv pk-pk 60 db channel separation 1khz signal, -5.2dbv 85 db 10khz signal, -5.2dbv 80 channel level matching 1khz signal, -5.2dbv +/-1 db power supply rejection ratio psrr 1khz, 100mvpk-pk 60 db 20khz, 100mv pk-pk 40
production data WM8903 w pd, rev 4.5, june 2012 11 single-ended stereo record from analogue microphones - in2l / in2r pins to adc output test conditions: l_mode = r_mode = 00b (single ended) lin_vol = rin_vol = 11111b (+28.3db) total signal path gain = +34.3db, incorporating 6db single-ended to differential conversion gain parameter symbol test conditions min typ max unit single-ended mic input full-scale signal level (for adc 0dbfs output) 0.019 -34.3 0.055 vrms dbv vpk-pk input resistance r in 10 12 k ? input capacitance c in 10 pf dc offset at adc output with adc_hpf_ena=0 11864 lsbs (24-bit) 47 lsbs (16-bit) signal to noise ratio snr a-weighted 73 dbfs total harmonic distortion thd -35dbv input -78 dbfs total harmonic distortion + noise thd+n -35dbv input -77 dbfs channel level matching 1khz signal, -35dbv +/-3 db power supply rejection ratio psrr 1khz, 100mvpk-pk 60 db 20khz, 100mv pk-pk 40 differential stereo record from analogue microphones - in1l+in2l / in1r+in2r pins to adc output test conditions: l_mode = r_mode = 10b (differential mic) lin_vol = rin_vol = 00111b (+30db) total signal path gain = +30db parameter symbol test conditions min typ max unit differential mic input full scale signal level in1l-in2l / in1r-in2r (for adc 0dbfs output) 0.032 -30 0.089 vrms dbv vpk-pk input resistance r in 100 120 k ? input capacitance c in 10 pf dc offset at adc output with adc_hpf_ena=0 189813 lsbs (24-bit) 742 lsbs (16-bit) signal to noise ratio snr a-weighted 75 dbfs total harmonic distortion thd -31dbv input -78 dbfs total harmonic distortion + noise thd+n -31dbv input -72 dbfs common mode rejection ratio cmrr 1khz, 100mvpk-pk 60 db channel separation 1khz signal, -31dbv 85 db 10khz signal, -31dbv 80 channel level matching 1khz signal, -31dbv +/-1 db psrr (referred to input) psrr 1khz, 100mvpk-pk 60 db 20khz, 100mv pk-pk 40
WM8903 production data w pd, rev 4.5, june 2012 12 pga and microphone boost parameter test conditions min typ max unit minimum pga gain setting l_mode/r_mode= 00b or 01b -1.55 db l_mode/r_mode= 10b +12 maximum pga gain setting l_mode/r_mode= 00b or 01b +28.28 db l_mode/r_mode= 10b +30 single-ended to differential conversion gain l_mode/r_mode= 00b +6 db pga gain accuracy l_mode/r_mode= 00b gain -1.55 to +6.7db -1 +1 db l_mode/r_mode= 00b gain +7.5 to +28.3db -1.5 +1.5 l_mode/r_mode= 1x gain +12 to +24db -1 +1 l_mode/r_mode= 1x gain +27 to +30db -1.5 +1.5 mute attenuation all modes of operation 88 db equivalent input noise l_mode/r_mode= 00b or 01b 114 828 vrms nv/ hz output signal path stereo playback to headphones - dac input to hpoutl+hpoutr pins with 15 ? load test conditions: hpoutl_vol = hpoutr_vol = 111001b (0db) parameter symbol test conditions min typ max unit output power (per channel) p o 1% thd r load = 30 ? 28 0.91 -0.76 mw vrms dbv 1% thd r load = 15 ? 30 0.67 -3.47 mw vrms dbv dc offset d c servo enabled, calibration complete. 0 +/-1.5 mv signal to noise ratio snr a-weighted 90 96 db total harmonic distortion thd r l =30 ? ; p o =2mw -93 db r l =30 ? ; p o =20mw -82 r l =15 ? ; p o =2mw -83 -72 r l =15 ? ; p o =20mw -83 total harmonic distortion + noise thd+n r l =30 ? ; p o =2mw -90 db r l =30 ? ; p o =20mw -82 r l =15 ? ; p o =2mw -81 -70 r l =15 ? ; p o =20mw -81 channel separation 1khz signal, 0dbfs 100 db 10khz signal, 0dbfs 85 channel level matching 1khz signal, 0dbfs +/-1 db power supply rejection ratio psrr 1khz, 100mv pk-pk 60 db 20khz, 100mv pk-pk 40
production data WM8903 w pd, rev 4.5, june 2012 13 stereo playback to line-out - dac input to lineoutl+lineoutr pins with 3.01k ? / 50pf load test conditions: lineoutl_vol = lineoutr_vol = 111001b (0db) parameter symbol test conditions min typ max unit full scale output signal level dac 0dbfs output at 0db volume 0.95 -0.446 2.69 1.0 0 2.83 1.05 0.424 2.97 vrms dbv vpk-pk dc offset dc servo enabled. calibration complete. 0 +/-1.5 mv signal to noise ratio snr a-weighted 90 95 db total harmonic distortion thd 3.01k ? load -86 -77 db total harmonic distortion + noise thd+n 3.01k ? load -84 -75 db channel separation 1khz signal, 0dbfs 100 db 10khz signal, 0dbfs 85 channel level matching 1khz signal, 0dbfs +/-1db db power supply rejection ratio psrr 1khz, 100mvpk-pk 60 db 20khz, 100mv pk-pk 40 stereo playback to differential line-out - dac input to lop+lon or rop+ron pins with 10k ? / 50pf load test conditions: spkr_lvol = spkr_rvol = 111001b (0db) parameter symbol test conditions min typ max full scale output signal level 0dbfs measured differentially 0.95 -0.446 2.69 1.0 0 2.83 1.05 0.424 2.97 vrms dbv vpk-pk common mode output level avdd/2 common mode output error +/-7 mv signal to noise ratio snr a-weighted 90 95 db total harmonic distortion thd -92 -82 db total harmonic distortion + noise thd+n -88 -80 db channel separation 1khz signal, 0dbfs 100 db 10khz signal, 0dbfs 85 channel level matching 1khz signal +/-1db db power supply rejection ratio psrr 1khz, 100mvpk-pk 60 db 20khz, 100mv pk-pk 40 output pgas (hp, line and differential line) parameter test conditions min typ max unit minimum pga gain setting -57 db maximum pga gain setting 6 db pga gain step size 1 db pga gain accuracy +6db to 0db -1.5 +1.5 db pga gain accuracy 0db to -57db -1 +1 db mute attenuation hpoutl/r 77 db lineoutl/r 79 differential line (lop-lor/rop-ron) 105 db
WM8903 production data w pd, rev 4.5, june 2012 14 bypass path differential stereo line input to stereo line output - in2l-in3l / in2r-in3r pins to lineoutl+lineoutr pins with 3.01k ? / 50pf load test conditions: l_mode = r_mode = 01b (differential line) lin_vol = rin_vol = 00101b (0db) lineoutl_vol = lineoutr_vol = 111001b (0db) total signal path gain = 0db parameter symbol test conditions min typ max unit maximum line input signal level applied to in2l or in2r 1.0 0 2.83 vrms dbv vpk-pk full scale output signal level 0.95 -0.446 2.69 1.0 0 2.83 1.05 0.424 2.97 vrms dbv vpk-pk signal to noise ratio snr a-weighted 85 97 dbv total harmonic distortion thd -1.0dbv input -92 -82 dbv total harmonic distortion + noise thd+n -1.0dbv input -89 -80 dbv channel separation 1khz signal, -1dbv 85 db 10khz signal, -1dbv 80 channel level matching 1khz signal, -1dbv +/-1 db power supply rejection ratio psrr 1khz, 100mvpk-pk 56 db 20khz, 100mv pk-pk 40
production data WM8903 w pd, rev 4.5, june 2012 15 charge pump parameter symbol test conditions min typ max unit charge pump start-up time 40 s external component requirements to achieve specified headphone output power and performance flyback capacitor (between cfb1 and cfb2 pins) c fb at 2v 1 f vpos capacitor at 2v 2 f vneg capacitor at 2v 2 f fll parameter symbol test conditions min typ max unit input frequency f ref fll_clk_ref_div = 00 0.032 13.5 mhz fll_clk_ref_div = 01 0.032 27 mhz lock time 2 ms free-running mode start-up time vmid enabled 100 ? s free-running mode frequency accuracy reference supplied initially +/-10 % no reference provided +/-30 % other parameters vmid reference parameter test conditions min typ max unit midrail reference voltage (vmid pin) ?3% avdd/2 +3% v microphone bias (for analogue electret condenser microphones) additional test conditions: micbias_ena=1, all parameters measured at the micbias pin parameter symbol test conditions min typ max unit bias voltage v micbias 3ma load current -5% 0.9avdd +5% v maximum source current i micbias 4 ma noise spectral density at 1khz 19 nv/ hz power supply rejection ratio psrr 1khz, 100mv pk-pk 50 db 20khz, 100mv pk-pk 70 micbias current detect function (see notes 1, 2) current detect threshold (microphone insertion) micdet_thr = 00 100 ? a current detect threshold (microphone removal) 15 delay time for current detect interrupt t det 1.25-15 ms micbias short circuit (hook switch) detect function (see notes 1, 2) short circuit detect threshold (button press) micshort_thr = 00 400 520 647 ? a short circuit detect hysteresis (see note 3) 50 minimum delay time for short circuit detect interrupt t short 40 ms short circuit detect measurement frequency 250 hz notes: 1. if avdd ? 1.8, current threshold values s hould be multiplied by (avdd/1.8)
WM8903 production data w pd, rev 4.5, june 2012 16 2. micbias current detect and short circuit (hook switch) detect functionality tested using gpio pin rather than by interrupt. 3. hysteresis = difference between butt on press and button release thresholds digital inputs / outputs parameter symbol test conditions min typ max unit input high level v ih 0.7 ? dbvdd v input low level v il 0.3 ? dbvdd v output high level v oh i oh = +1ma 0.9 ? dbvdd v output low level v ol i ol = -1ma 0.1 ? dbvdd v
production data WM8903 w pd, rev 4.5, june 2012 17 power consumption the WM8903 power consumption is dependent on many parameters. most significantly, it depends on supply voltages, sample rates, mode of operation, and output loading. the power consumption on each s upply rail varies approximately with the square of the voltage. power consumption is greater at fast sample rates than at slower ones. when the digital audio interface is operating in master mode, the dbvdd cu rrent is significantly greater than in slave mode. (note also that power savings can be made by usi ng mclk as the bclk source in slave mode.) the output load conditions (impedance, capacitance and inductance) can al so impact significantly on the device power consumption. common test conditions unless otherwise stated, the following test conditions apply throughout the following sections: ? ambient temperature = +25c ? audio signal = quiescent (zero amplitude) ? sample rate = 44.1khz ? mclk = 12mhz ? audio interface mode = master (lrclk_dir=1, bclk_dir=1) ? clk_src_sel = 0 (system clock comes direct from mclk, not from fll) additional, variant test conditions are quoted within the relevant sections below. where applicable, power dissipated in the headphone or line loads is included. power consumption measurements single-ended stereo line record - in1l/r, in2l/r or in3l/r pins to adc output. test conditions: l_mode = r_mode = 00b (single ended) lin_vol = rin_vol = 00000b (-1.55db) adc_osr128 = 0 variant test conditions avdd dcvdd dbvdd cpvdd total v ma v ma v ma v ma mw 44.1khz sample rate 1.8 3.60 1.2 1.04 1.8 0.10 1.8 0.00 7.9 8khz sample rate 1.8 3.40 1.2 0.50 1.8 0.03 1.8 0.00 6.8 differential stereo record from analogue microphones - in1l/r, in2l/r or in3l/r pins to adc out. test conditions: l_mode = r_mode = 10b (differential mic) adc_osr128 = 0 variant test conditions avdd dcvdd dbvdd cpvdd total v ma v ma v ma v ma mw 44.1khz sample rate 1.8 3.60 1.2 1.00 1.8 0.10 1.8 0.00 7.9 8khz sample rate 1.8 3.40 1.2 0.50 1.8 0.03 1.8 0.00 6.8
WM8903 production data w pd, rev 4.5, june 2012 18 stereo playback to headphones - dac input to hpoutl+hpoutr pins with 30 ? load. test conditions dacbias_sel = 01b (normal bias x 0.5) dacvmid_bias_sel = 11b (normal bias x 0.75) pga_bias = 011b (normal bias x 0.5) cp_dyn_pwr = 1b (charge pump controlled by real-time audio level) variant test conditions avdd dcvdd dbvdd cpvdd total v ma v ma v ma v ma mw slave mode, 44.1khz sample rate, quiescent 1.8 1.60 1.2 0.76 1.8 0.00 1.8 0.41 4.5 master mode, 44.1khz sample rate, quiescent 1.8 1.60 1.2 0.76 1.8 0.09 1.8 0.41 4.7 master mode, 44.1khz, p o = 0.1mw/channel 1.8 1.60 1.2 0.90 1.8 0.09 1.8 1.85 7.5 master mode, 44.1khz, p o = 1mw/channel 1.8 1.60 1.2 0.92 1.8 0.09 1.8 5.77 14.5 master mode, 8khz sample rate, quiescent 1.8 1.60 1.2 0.65 1.8 0.03 1.8 0.41 4.4 master mode, 8khz, p o = 0.1mw/channel 1.8 1.60 1.2 0.71 1.8 0.03 1.8 1.85 7.1 stereo playback to line-out - dac input to lineoutl+lineoutr or hpoutl+hpoutr pins with 3.01k ? / 50pf load test conditions: cp_dyn_pwr = 1b (charge pump controlled by real-time audio level) variant test conditions avdd dcvdd dbvdd cpvdd total v ma v ma v ma v ma mw 44.1khz sample rate 1.8 1.95 1.2 0.76 1.8 0.09 1.8 0.32 5.2 8khz sample rate 1.8 1.95 1.2 0.68 1.8 0.03 1.8 0.32 4.9 stereo analogue bypass to headphones - in1l/r, in2l/r or in3l/r pins to hpoutl+hpoutr pins with 30 ? load. test conditions: audi o interface disabled note that the analogue bypass configuration does not benefit from the class w dynamic control, and the power consumption is greater in this case than the dac to line-out case. see ?charge pump? section. variant test conditions avdd dcvdd dbvdd cpvdd total v ma v ma v ma v ma mw quiescent 1.8 1.46 1.2 0.12 1.8 0.00 1.8 1.54 5.5 p o = 0.1mw/channel 1.8 1.46 1.2 0.12 1.8 0.00 1.8 4.54 11.0 off test conditions: no clocks applied variant test conditions avdd dcvdd dbvdd cpvdd total v ma v ma v ma v ma mw none 1.8 0.01 1.2 0.012 1.8 0.003 1.8 0.005 0.047
production data WM8903 w pd, rev 4.5, june 2012 19 signal timing requirements common test conditions unless otherwise stated, the following test conditions apply throughout the following sections: ? ambient temperature = +25c ? dcvdd = 1.2v ? dbvdd = avdd = cpvdd = 1.8v ? dgnd = agnd = cpgnd = 0v additional, specific test c onditions are given within t he relevant sections below. master clock figure 1 master clock timing master clock timing parameter symbol test conditions min typ max unit mclk cycle time t mclky mclkdiv2=1 40 ns mclkdiv2=0 80 ns mclk cycle time t mclky dcvdd ?? 1.62v mclkdiv2=0 54.25 ns mclk duty cycle t mclkds 60:40 40:60
WM8903 production data w pd, rev 4.5, june 2012 20 audio interface timing master mode figure 2 audio interface timing ? master mode audio interface timing ? master mode parameter symbol min typ max unit lrc propagation delay from bclk falling edge t dl 10 ns adcdat propagation delay from bclk falling edge t dda 10 ns dacdat setup time to bclk rising edge t dst 10 ns dacdat hold time from bclk rising edge t dht 10 ns
production data WM8903 w pd, rev 4.5, june 2012 21 slave mode figure 3 audio interface timing ? slave mode audio interface timing ? slave mode parameter symbol min typ max unit bclk cycle time t bcy 50 ns bclk pulse width high t bch 20 ns bclk pulse width low t bcl 20 ns lrc set-up time to bclk rising edge t lrsu 10 ns lrc hold time from bclk rising edge t lrh 10 ns dacdat hold time from bclk rising edge t dh 10 ns adcdat propagation delay from bclk falling edge t dd 30 ns dacdat set-up time to bclk rising edge t ds 20 ns note: bclk period must always be greater than or equal to mclk period.
WM8903 production data w pd, rev 4.5, june 2012 22 tdm mode in tdm mode, it is important that two devices to not attempt to drive the adcdat pin simultaneously. the timing of the WM8903 adcdat pin tri-stating at the start and end of the data transmission is described below. figure 4 audio interface timing ? tdm mode audio interface timing ? tdm mode parameter symbol min typ max unit adcdat setup time from bclk falling edge 4 ns adcdat release time from bclk falling edge 25 ns
production data WM8903 w pd, rev 4.5, june 2012 23 control interface timing figure 5 control interface timing control interface timing parameter symbol min typ max unit sclk frequency 526 khz sclk low pulse-width t 1 1.3 s sclk high pulse-width t 2 600 ns hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns sdin, sclk rise time t 6 300 ns sdin, sclk fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 9 900 ns pulse width of spikes that will be suppressed t ps 0 5 ns
WM8903 production data w pd, rev 4.5, june 2012 24 digital filter characteristics parameter test conditions min typ max unit adc filter passband +/- 0.05db 0 0.454 fs -6db 0.5fs passband ripple +/- 0.05 db stopband 0.546s stopband attenuation f > 0.546 fs -60 db dac normal filter passband +/- 0.05db 0 0.454 fs -6db 0.5 fs passband ripple 0.454 fs +/- 0.03 db stopband 0.546 fs stopband attenuation f > 0.546 fs -50 db dac sloping stopband filter passband +/- 0.03db 0 0.25 fs +/- 1db 0.25 fs 0.454 fs -6db 0.5 fs passband ripple 0.25 fs +/- 0.03 db stopband 1 0.546 fs 0.7 fs stopband 1 attenuation f > 0.546 fs -60 db stopband 2 0.7 fs 1.4 fs stopband 2 attenuation f > 0.7 fs -85 db stopband 3 1.4 fs stopband 3 attenuation f > 1.4 fs -55 db dac filters adc filters mode group delay mode group delay normal 16.5 / fs normal 16.5 / fs sloping stopband 18 / fs terminology 1. stop band attenuation (db) ? the degree to which the frequency spectrum is attenuated (outside audio band) 2. pass-band ripple ? any variation of t he frequency response in the pass-band region
production data WM8903 w pd, rev 4.5, june 2012 25 dac filter responses figure 6 dac filter response for clk_sys_mode = 10b (clock is 250 x fs related) dac_sb_filt = 1b (sloping stopband filter) sample rate ? 24khz figure 7 dac filter response for clk_sys_mode = 00b or 01b dac_sb_filt = 1b (sloping stopband filter) sample rate ? 24khz figure 8 dac filter response for clk_sys_mode = 10b (clock is 250 x fs related) dac_sb_filt = 0b (normal filter) sample rate > 24khz (except 88.2khz) figure 9 dac filter response for clk_sys_mode = 00b or 01b dac_sb_filt = 0b (normal filter) sample rate > 24khz
WM8903 production data w pd, rev 4.5, june 2012 26 figure 10 dac filter response for clk_sys_mode = 01b (clock is 272 x fs related) dac_sb_filt = 0b (normal filter) sample rate = 88.2khz adc filter responses figure 11 adc filter response for clk_sys_mode = 10b (not applicable to 88.2/96khz) figure 12 adc filter response for clk_sys_mode = 00b or 01b
production data WM8903 w pd, rev 4.5, june 2012 27 figure 13 adc filter passband ripple for clk_sys_mode = 10b adc high pass filter responses ma gnitude( db) 1 2.6923 7.2484 19.515 52.54 141.45 380 .83 1.0253k 2.7605k 7.432k 20.009k -11.736 -10.562 -9.3883 -8.2145 -7.0407 -5.8669 -4.6931 -3.5193 -2.3455 -1.1717 2.1246m hpf _response.res magnitude(db) hpf_response2.res magnitude(db) hpf _response2.res#1 magnitude(db) 2 5.0248 12.624 31.716 79.683 200.19 502.96 1.2636k 3.1747k 7.9761k 20.039k -83.352 -75.017 -66.682 -58.347 -50.012 -41.677 -33.342 -25.007 -16.672 -8.3373 -2.3338m figure 14 adc digital high pass filter frequency response (48khz, hi-fi mode, adc_hpf_cut[1:0]=00) figure 15 adc digital high pass filter ripple (48khz, voice mode, adc_hpf_cut=01, 10 and 11) the plots shown are for 48khz. for other sample rates, the plots should be scaled accordingly.
WM8903 production data w pd, rev 4.5, june 2012 28 de-emphasis filter responses magnitude(db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 5000 10000 15000 20000 frequency (hz) magnitude(db) -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 frequency (hz) figure 16 de-emphasis digital filter response (32khz) figure 17 de-emphasis error (32khz) magnitude(db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 5000 10000 15000 20000 25000 frequency (hz) magnitude(db) -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 5000 10000 15000 20000 25000 frequency (hz) figure 18 de-emphasis digital filter response ( 44.1khz) figure 19 de-emphasis error (44.1khz) magnitude(db) -12 -10 -8 -6 -4 -2 0 0 5000 10000 15000 20000 25000 30000 frequency (hz) magnitude(db) -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0 5000 10000 15000 20000 25000 30000 frequency (hz) figure 20 de-emphasis digital filter response (48khz) figure 21 de-emphasis error (48khz)
production data WM8903 w pd, rev 4.5, june 2012 29 device description introduction the WM8903 is a high performance ultra-low pow er stereo codec optimised for portable audio applications. flexible analogue interfaces and powerful digital signal processing (dsp) make it ideal for small portable devices. the WM8903 supports up to 6 analogue audio inputs. one pair of single-ended or differential microphone/line inputs is selected as the adc input s ource. an integrated bias reference is provided to power standard electret microphones. a two-channel digital microphone interface is also s upported, with direct input to the dsp core bypassing the adcs. two pairs of ground-referenced class w headphone / line outputs are provided; these are powered from an integrated charge pump, enabling high quality, power efficient headphone playback without any requirement for dc blocking capacitors. a dc serv o circuit is available fo r dc offset correction, thereby suppressing pops and reduci ng power consumption. two differential line outputs are also provided; these are also capabl e of driving external speaker drivers. ground loop feedback is available on the ground-referenced headphone and line output s, providing rejection of noise on the ground connections. all outputs use wolfson s ilentswitch? technology for pop and click suppression. the stereo adcs and dacs are of hi-fi quality, usi ng a 24-bit low-order oversampling architecture to deliver optimum performance. a high pass filter is available in the adc path for removing dc offsets and suppressing low frequency noise such as mechani cal vibration and wind noise. a digital mixing path from the adc to the dac provides a si detone of enhanced quality during voice calls. dac soft mute and un-mute is available for pop-free music playback. the integrated dynamic range controller (drc) provi des further processing capability of the digital audio paths. the drc provides compression and signal level control to improve the handling of unpredictable signal levels. ?anti-clip? and ?quick re lease? algorithms improve intelligibility in the presence of transients and impulsive noises. the WM8903 has a highly flexible digital audio interf ace, supporting a number of protocols, including i2s, dsp, msb-first left/right justified, and can operate in master or slave modes. pcm operation is supported in the dsp mode. a-law and ? -law companding are also supported. time division multiplexing (tdm) is available to allow multiple devices to stream data simultaneously on the same bus, saving space and power. the system clock clk_sys provides clocking for the adcs, dacs, dsp core, digital audio interface and other circuits. clk_sys can be derived directly from the mclk pin or via an integrated fll, providing flexibility to support a wide range of cl ocking schemes. typical portable system mclk frequencies, and sample rates from 8khz to 96khz are all supported. the clocking circuits are configured automatically from the sample rate (fs) and from the clk_sys / fs ratio. the integrated fll can be used to generate clk_sys from a wide variety of different reference sources and frequencies. the fll can accept a wi de range of reference frequencies, which may be high frequency (e.g. 13mhz) or low frequency (eg. 32.768k hz). the fll is tolerant of jitter and may be used to generate a stable clk_sys from a less stable input signal. the integrated fll can be used as a free-running oscillator, enabling autonomous clocking of the charge pump and dc servo if required. the WM8903 uses a standard 2-wire control interface, providing full software control of all features, together with device register readback. an int egrated control write sequencer enables automatic scheduling of control sequences; co mmonly-used signal configurations may be selected using ready- programmed sequences, including time-optimised c ontrol of the WM8903 pop suppression features. it is an ideal partner for a wide range of industr y standard microprocessors, controllers and dsps. unused circuitry can be di sabled under software control, in order to save power; low leakage currents enable extended standby/off time in portable battery-powered applications. up to 5 gpio pins may be configured for miscellaneous input/output functions such as button/accessory detect inputs, or for clock, syst em status, or programmable logic level output for control of additional external ci rcuitry. interrupt logic, stat us readback and de-bouncing options are supported within this functionality.
WM8903 production data w pd, rev 4.5, june 2012 30 analogue input signal path the WM8903 has six analogue input pi ns, which may be used to suppor t connections to multiple microphone or line input sources. the input multip lexer on the left and right channels can be used to select different configurations for each of t he input sources. the anal ogue input paths can support line and microphone inputs, in single-ended and different ial modes. the input stage can also provide common mode noise rejection in some configurations. the left and right analogue input channels are routed to the analogue to digita l converters (adcs). there is also a bypass path for each channel, enabling the signal to be routed directly to the output mixers. the WM8903 input signal paths and control registers are illustrated in figure 22. agnd single-ended (inverting) mode: gain -1.55db to +28.5db, non-linear steps differential line mode: gain -1.55db to +28.5db, non-linear steps differential microphone mode: gain +12db to +30db, 3db steps mux in1l in3l in2l - + l_mode l_ip_sel_n l_ip_sel_p inl_ena inl_cm_ena lin_mute lin_vol avdd vmid bypassl mux in1r in3r in2r - + r_mode r_ip_sel_n r_ip_sel_p inr_ena inr_cm_ena rin_mute rin_vol vmid bypassr adc l adc r single-ended (inverting) mode: gain -1.55db to +28.5db, non-linear steps differential line mode: gain -1.55db to +28.5db, non-linear steps differential microphone mode: gain +12db to +30db, 3db steps figure 22 block diagram for input signal path
production data WM8903 w pd, rev 4.5, june 2012 31 input pga enable the input pgas (programmable gain amplifiers) and multiplexers are enabled using register bits inl_ena and inr_ena, as shown in table 1. register address bit label default description r12 (0ch) power management 0 1 inl_ena 0 left input pga enable 0 = disabled 1 = enabled 0 inr_ena 0 right input pga enable 0 = disabled 1 = enabled table 1 input pga enable to enable the input pgas, the reference voltage vm id and the bias current must also be enabled. see ?reference voltages and master bias? for det ails of the associated controls vmid_res and bias_ena. input pga configuration the analogue input channels can each be configured in three different modes, which are as follows: ? single-ended mode (inverting) ? differential line mode ? differential mic mode the mode is selected by the l_mode and r_mo de fields for the left and right channels respectively. the input pins are selected using the l_ip_sel_n and l_ip_sel_p fields for the left channel and the r_ip_sel_n and r_ip_sel_p fo r the right channel. in single-ended mode, l_ip_sel_n alone determines the left input pin, and the r_ip_sel_n determines the right input pin. the three modes are illustrated in figure 23, figure 24 and figure 25. it should be noted that the available gain and input impedance varies between configurati ons (see also ?electrical characteristics?). the input impedance is constant with pga gain setting. the input pga modes are selected and configured usi ng the register fields described in table 2.
WM8903 production data w pd, rev 4.5, june 2012 32 register address bit label default description r46 (2eh) analogue left input 1 5:4 l_ip_sel_n [1:0] 00 in single-ended or differential line modes, this field selects the input pin for the inverting side of the left input path. in differential mic mode, this field selects the input pin for the non- inverting side of the left input path. 00 = in1l 01 = in2l 1x = in3l 3:2 l_ip_sel_p [1:0] 01 in single-ended or differential line modes, this field selects the input pin for the non-inverting side of the left input path. in differential mic mode, this field selects the input pin for the inverting side of the left input path. 00 = in1l 01 = in2l 1x = in3l 1:0 l_mode [1:0] 00 sets the mode for the left analogue input: 00 = single-ended 01 = differential line 10 = differential mic 11 = reserved r47 (2fh) analogue right input 1 5:4 r_ip_sel_n [1:0] 00 in single-ended or differential line modes, this field selects the input pin for the inverting side of the right input path. in differential mic mode, this field selects the input pin for the non- inverting side of the right input path. 00 = in1r 01 = in2r 1x = in3r 3:2 r_ip_sel_p [1:0] 01 in single-ended or differential line modes, this field selects the input pin for the non-inverting side of the right input path. in differential mic mode, this field selects the input pin for the inverting side of the right input path. 00 = in1r 01 = in2r 1x = in3r 1:0 r_mode [1:0] 00 sets the mode for the right analogue input: 00 = single-ended 01 = differential line 10 = differential mic 11 = reserved table 2 input pga mode selection
production data WM8903 w pd, rev 4.5, june 2012 33 single-ended input the single-ended pga configuration is illustrated in figure 23 for the left channel. the available gain in this mode is from -1.55db to +28. 5db in non-linear steps. the input impedance is 12k ? . the input to the adc is phase inverted with respect to the selected input pin. different input pins can be selected in the same mode by altering the l_ip_sel_n field. the equivalent configuration is also avail able on the right channel; this can be selected independently of the left channel mode. bypassl in1l in3l in2l - + l_ip_sel_n -1.55db to +28.5db, non-linear steps inl_ena lin_mute lin_vol adc l vmid m u x single-ended (inverting) mode (l_mode = 00) figure 23 single ended mode differential line input the differential line pga configuration is illustra ted in figure 24 for the left channel. the available gain in this mode is from -1.55db to +28. 5db in non-linear steps. the input impedance is 12k ? . the input to the adc is in phase with the input pin selected by l_ip_sel_p. the input to the adc is phase inverted with respect to the input pin selected by l_ip_sel_n. as an option, common mode noise rejection can be prov ided in this pga configuration, as illustrated in figure 24. this is enabled using the register bits defined in table 5. the equivalent configuration is also avail able on the right channel; this can be selected independently of the left channel mode. bypassl in1l in3l in2l - + l_ip_sel_n inl_ena lin_mute lin_vol adc l m u x l_ip_sel_p m u x differential line mode (l_mode = 01) -1.55db to +28.5db, non-linear steps inl_cm_ena + - figure 24 differential line mode
WM8903 production data w pd, rev 4.5, june 2012 34 differential microphone input the differential mic pga configuration is illustra ted in figure 25 for the left channel. the available gain in this mode is from +12db to +30db in 3db linear steps. the input impedance is 120k ? . the input to the adc is in phase with the input pin selected by l_ip_sel_n. the input to the adc is phase inverted with respect to the input pin selected by l_ip_sel_p. note that the inverting input pin is selected using l_ip_sel_p and the non-inverting input pin is selected using l_ip_sel_n. this is not the same as for the differential line mode. the equivalent configuration is also avail able on the right channel; this can be selected independently of the left channel mode. figure 25 differential microphone mode input pga gain control the volume control gain for the left and ri ght channels be independently controlled using the lin_vol and rin_vol register fields as descri bed in table 3. the available gain range varies according to the selected pga mode as detailed in table 4. note that the value ?00000? must not be used in differential mic mode, as the pga will not function correctly under this setting. in single- ended mode (l_mode / r_mode = 00b), the conversion from single-ended to differential within the WM8903 adds a further 6db of gain to the signal path. each input channel can be independently muted using linmute and rinmute. it is recommended to not adjust the gain dynamica lly whilst the signal path is enabled; the signal should be muted at the input or output stage prior to adjusting the volume control. register address bit label default description r44 (2ch) analogue left input 0 7 linmute 1 left input pga mute 0 = not muted 1 = muted 4:0 lin_vol [4:0] 00101 left input pga volume (see table 4 for volume range) r45 (2dh) analogue right input 0 7 rinmute 1 right input pga mute 0 = not muted 1 = muted 4:0 rin_vol [4:0] 00101 right input pga volume (see table 4 for volume range) table 3 input pga volume control
production data WM8903 w pd, rev 4.5, june 2012 35 lin_vol [4:0], rin_vol [4:0] gain ? single-ended mode / differential line mode gain ? differential mic mode 00000 -1.55 db not valid 00001 -1.3 db +12 db 00010 -1.0 db +15 db 00011 -0.7 db +18 db 00100 -0.3 db +21 db 00101 0.0 db +24 db 00110 +0.3 db +27 db 00111 +0.7 db +30 db 01000 +1.0 db +30 db 01001 +1.4 db +30 db 01010 +1.8 db +30 db 01011 +2.3 db +30 db 01100 +2.7 db +30 db 01101 +3.2 db +30 db 01110 +3.7 db +30 db 01111 +4.2 db +30 db 10000 +4.8 db +30 db 10001 +5.4 db +30 db 10010 +6.0 db +30 db 10011 +6.7 db +30 db 10100 +7.5 db +30 db 10101 +8.3 db +30 db 10110 +9.2 db +30 db 10111 +10.2 db +30 db 11000 +11.4 db +30 db 11001 +12.7 db +30 db 11010 +14.3 db +30 db 11011 +16.2 db +30 db 11100 +19.2 db +30 db 11101 +22.3 db +30 db 11110 +25.2 db +30 db 11111 +28.3 db +30 db table 4 input pga volume range
WM8903 production data w pd, rev 4.5, june 2012 36 input pga common mode amplifier in differential line mode only, a common mode am plifier can be enabled as part of the input pga circuit. this feature provides approximately 20db reduction in common mode noise on the differential input, which can reduce problematic interference. since the adc has di fferential signal inputs, it has an inherent immunity to common mode noise (see ?ele ctrical characteristics?) however, the presence of common mode noise can limit the usable si gnal range of the adc path; enabling the common mode amplifier can solve this issue. it should be noted that the common mode amplifier consumes additional power and can also add its own noise to the input signal. fo r these reasons, it is recommended that the common mode amplifier is only enabled if there is a known s ource of common mode interference. the common mode amplifier is controlled by the inl_cm_ena and inr_cm_ena fields as described in table 5. although the common mode amplifier may be enabled regardless of the input pga mode, its function is only effective in the differential line mode configuration. register address bit label default description r46 (2eh) analogue left input 1 6 inl_cm_ena 1 left input pga common mode rejection enable 0 = disabled 1 = enabled (only available for l_mode=01 ? differential line) r47 (2fh) analogue right input 1 6 inr_cm_ena 1 right input pga common mode rejection enable 0 = disabled 1 = enabled (only available for r_mode=01 ? differential line) table 5 common mode amplifier enable
production data WM8903 w pd, rev 4.5, june 2012 37 electret condenser microphone interface electret condenser microphones may be connected as single-ended or differential inputs to the input pgas described in the ?analogue input signal path ? section. the WM8903 provides a low-noise reference voltage suitable for bias ing electret condenser microphones. the micbias reference is provided on the micbias pin. this reference voltage is enabled by setting the micbias_ena register bit, as defined in table 6. register address bit label default description r6 (06h) mic bias control 0 0 micbias_ena 0 micbias enable 0 = disabled 1 = enabled table 6 micbias control micbias current detect a micbias current detect function is provided for ex ternal accessory detection. this is provided in order to detect the insertion/removal of a mi crophone or the pressing/releasing of the microphone ?hook? switch; these events will cause a signific ant change in micbias current flow, which can be detected and used to generate a signal to the host processor. the micbias current detect function is enabled by setting the micdet_ena register bit. when this function is enabled, two current thresholds can be defined, using the micdet_thr and micshort_thr registers. when a change in micbias current which crosses either threshold is detected, then an interrupt event can be generated. in a typical application, accessory insertion would be detected when the micbias current exceeds micdet_thr, and microphone hookswitch operation would be detected when the micbias current exceeds micshort_thr. the current detect threshold functi ons are both inputs to the interr upt control circuit and can be used to trigger an interrupt event when either threshold is crossed. both events can also be indicated as an output on a gpio pin - see ?general purpose input/output (gpio)?. the current detect thresholds are enabled and contro lled using the registers described in table 7. performance parameters for this circ uit block can be found in the ?electrical characteristics? section. hysteresis and filtering is also provided in the bot h current detect circuits to improve reliability in conditions where ac current spikes are present due to ambient noise conditions. these features are described in the following section. further guidanc e on the usage of the micbias current monitoring features is also described in the following pages. register address bit label default description r6 (06h) mic bias control 0 5:4 micdet_thr [1:0] 00 micbias current detect insertion threshold 00 = 0.063ma 01 = 0.26ma 10 = 0.45ma 11 = 0.635ma values are scaled with avdd. figures shown are based on avdd=1.8v. 3:2 micshort_th r [1:0] 00 micbias short circuit button push threshold 00 = 0.52ma 01 = 0.77ma 10 = 1.2ma 11 = 1.43ma values are scaled with avdd. figures shown are based on avdd=1.8v.
WM8903 production data w pd, rev 4.5, june 2012 38 register address bit label default description 1 micdet_ena 0 micbias current and short circuit detect enable 0 = disabled 1 = enabled table 7 micbias current detect micbias current detect filtering the function of the filtering is to ensure that ac current spikes caused by ambient noise conditions near the microphone do not lead to incorrect signalling of the microphone insertion/removal status or the microphone hookswitch status. hysteresis on the current thresholds is provided; this means that a different current threshold is used to detect microphone insertion and microphone removal. si milarly, a different current threshold is used to detect hookswitch press and hookswtich release. digital filtering of the hookswitch status ensures that the micbias short ci rcuit detection event is only signalled if the micshort_thr threshol d condition has been met for 10 consecutive measurements. in a typical application, microphone insertion woul d be detected when the micbias current exceeds the current detect threshold set by micdet_thr. when the micdet_inv interrupt polarity bit is set to 0, then microphone insertion detection will cause the micdet_eint interrupt status register to be set. for detection of microphone removal, the micde t_inv bit should be set to 1. when the micdet_inv interrupt polarity bit is set to 1, then microphone removal detection will cause the micdet_eint interrupt status register to be set. the detection of these events is bandwidth limited for best noise rejection, and is subject to detection delay time t det , as specified in the ?electrical characte ristics?. provided that the micdet_thr field has been set appropriately, each insertion or removal event is guaranteed to be detected within the delay time t det . it is likely that the microphone socket contacts will have mechanical ?bounce? when a microphone is inserted or removed, and hence the resultant contro l signal will not be a clean logic level transition. since t det has a range of values, it is possible that the interrupt will be generated before the mechanical ?bounce? has ceased. h ence after a mic insertion or removal has been detected, a time delay should be applied before re-configuring the micdet_in v bit. the maximum possible mechanical bounce times for mic insertion and removal must be understood by the software programmer. utilising a gpio pin to monitor the steady stat e of the microphone detecti on function does not change the timing of the detection mechanism , so there will also be a delay t det before the signal changes state. it may be desirable to implement de-bounce in the host processor when monitoring the state of the gpio signal. microphone hook switch operation is detected when t he micbias current exceeds the short circuit detect threshold set by micshort_thr. using the digital filtering, the hook switch detection event is only signalled if the micshort_thr thres hold condition has been me t for 10 consecutive measurements. when the micshrt_inv interrupt polarity bit is se t to 0, then hook switch operation will cause the micshrt_eint interrupt status register to be set. for detection of microphone removal, the mics hrt_inv bit should be set to 1. when the micshrt_inv interrupt polarity bit is set to 1, then hook switch release will cause the micshrt_eint interrupt status register to be set.
production data WM8903 w pd, rev 4.5, june 2012 39 the hook switch detection measurement frequency and the detection delay time t short are detailed in the ?electrical characteristics? section. the WM8903 interrupt function is described in the ?int errupts? section. example control sequences for configuring the interrupts functions for micbi as current detection events are described in the ?applications information? section. a clock is required for the digital filtering function. this requires: ? mclk is present ? clk_sys_ena = 1 ? wsmd_clk_ena register address bit label default description r22 (16h) clock rates 2 2 clk_sys_ena 0 system clock enable 0 = disabled 1 = enabled r108 (6ch) write sequencer 0 8 wsmd_clk_en a 0 write sequencer / mic detect clock enable. 0 = disabled 1 = enabled table 8 micbias current detect clocking any micbias current detect event (accessory insert ion/removal or hookswitch press/release) which happens while one or more of the clocking criteria is not satisfied (for example during a low power mode where the cpu has disabled mclk) will still be detected, but only after the clocking conditions are met. an example is illustrated in figure 26, where the mic is inserted while mclk is stopped. figure 26 micbias detection events without mclk microphone hook switch detection the possibility of spurious hook switch interrupts due to ambient noise condi tions can be removed by careful understanding of the microphone behaviour under extremely high sound pressure levels or during mechanical shock, and by correct selection of the micbias resistor value; these factors will affect the level of the micbias ac current spikes.
WM8903 production data w pd, rev 4.5, june 2012 40 in applications where the current detect threshold is close to the level of the current spikes, the probability of false detections is reduced by the hysteresis and digital filtering described above. note that the filtering algorithm provides only limited rejection of very high current spikes at frequencies less than or equal to the hook switch detect measurement frequency, or at frequencies equal to harmonics of the hook switch detect measurement frequency. the micbias hook switch digital filtering is illu strated in figure 27. example control sequences for configuring the interrupts functions for micbi as current detection events are described in the ?applications information? section. figure 27 micbias hook switch detect filtering digital microphone interface the WM8903 supports a two-channel digital micr ophone interface. the two-channel audio data is multiplexed on the dmic_dat input and clocked by the dmic_lr output. the digital microphone input, dmic_dat, is provi ded on the gpio2/dmic_dat pin. the associated clock, dmic_lr, is provided on the gpio1/dmic_lr pin. the digital microphone input is selected as input by setting the adc_dig_mic bit. when the digital microphone input is selected, the adc input is bypassed. the digital microphone interface c onfiguration is illustrated in figure 28. note that that care must be taken to ensure that the respective digital l ogic levels of the microphone are compatible with the digital input thresholds of the WM8903. the digital input thresholds are referenced to dbvdd, as defined in ?electrical characteristics?. it is recommended to power the digital microphones from the sa me dbvdd supply as WM8903.
production data WM8903 w pd, rev 4.5, june 2012 41 figure 28 digital microphone interface control when gpio1 is configured as dmic_lr clock output, the WM8903 outputs a clock which supports digital mic operation at a multiple of the a dc sampling rate, in the range 1-3mhz. the adc and record path filters must be enabled and the adc sa mpling rate must be set in order to ensure correct operation of all dsp functions associated wi th the digital microphone. volume control for the digital microphone interface signals is prov ided using the adc volume control. see ?analogue-to-digital converter (adc)? for det ails of the adc enable and volume control functions. see ?general purpose input/output (gpi o)? for details of configuring the dmic_lr and dmic_dat functions. see ?clocking and sample rate s? for the details of the supported clocking configurations. when gpio2/dmic_dat is configured as dmic_dat input, then this pin is the digital microphone input. up to two microphones can share this pin; the two microphones are interleaved as illustrated in figure 29. the digital microphone interface requires that mic1 transmits a data bit each time that dmic_lr is high, and mic2 transmits when dmic_lr is lo w. the WM8903 samples the digital microphone data in the middle of each dmic_lr clock phase. each microphone must tri-state its data output when the other microphone is transmitting. figure 29 digital microphone interface timing the digital microphone interface control fields are described in table 9.
WM8903 production data w pd, rev 4.5, june 2012 42 register address bit label default description r164 (a4h) clock rate test 4 9 adc_dig_mic 0 enables digital microphone mode. 0 = audio dsp input is from adc 1 = audio dsp input is from digital microphone interface table 9 digital microphone interface control note that, in addition to setting the adc_dig_ mic bit as described in table 9, the pins gpio1/dmic_lr and gpio2/dmic_dat must also be configured to provide the digital microphone interface function. see ?general pur pose input/output (gpio)? for details. analogue-to-digital converter (adc) the WM8903 uses two 24-bit, 128x oversampled sigm a-delta adcs. the use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. an oversample rate of 64x can also be supported - see ?clocking and sample rates? for details. the adc full-scale input level is proportional to avdd - see ?electrical characteristics?. any input signal greater than full scale may overload the adc and cause distortion. the adcs are enabled by the adcl_e na and adcr_ena register bits. register address bit label default description r18 (12h) power management 6 1 adcl_ena 0 left adc enable 0 = disabled 1 = enabled 0 adcr_ena 0 right adc enable 0 = disabled 1 = enabled table 10 adc enable control adc digital volume control the output of the adcs can be digitally amplif ied or attenuated over a range from -71.625db to +17.625db in 0.375db steps. the volume of each c hannel can be controlled s eparately. the gain for a given eight-bit code is detailed in table 12. the adc_vu bit controls the loading of digital volu me control data. when adc_vu is set to 0, the adcl_vol or adcr_vol control data is loaded into the respective control register, but does not actually change the digital gain setting. both left and right gain settings are updated when a 1 is written to adc_vu. this makes it possible to update the gain of both channels simultaneously.
production data WM8903 w pd, rev 4.5, june 2012 43 register address bit label default description r36 (24h) adc digital volume left 8 adcvu n/a adc volume update writing a 1 to this bit causes left and right adc volume to be updated simultaneously (write-only register) 7:0 adcl_vol [7:0] 1100_0000 (0db) left adc digital volume 00h = mute 01h = -71.625db 02h = -71.250db ? (0.375db steps) c0h = 0db ? (0.375db steps) efh to ffh = +17.625db (see table 12 for volume range) r37 (25h) adc digital volume right 8 adcvu n/a adc volume update writing a 1 to this bit causes left and right adc volume to be updated simultaneously (write-only register) 7:0 adcr_vol [7:0] 1100_0000 (0db) right adc digital volume 00h = mute 01h = -71.625db 02h = -71.250db ? (0.375db steps) c0h = 0db ? (0.375db steps) efh to ffh = +17.625db (see table 12 for volume range) table 11 adc digital volume control
WM8903 production data w pd, rev 4.5, june 2012 44 adcl_vol or adcr_vol volume (db) adcl_vol or adcr_vol volume (db) a dcl_vol or adcr_vol volume (db) a dcl_vol or adcr_vol volume (db) 0h mute 40h -48.000 80h -24.000 c0h 0.000 1h -71.625 41h -47.625 81h -23.625 c1h 0.375 2h -71.250 42h -47.250 82h -23.250 c2h 0.750 3h -70.875 43h -46.875 83h -22.875 c3h 1.125 4h -70.500 44h -46.500 84h -22.500 c4h 1.500 5h -70.125 45h -46.125 85h -22.125 c5h 1.875 6h -69.750 46h -45.750 86h -21.750 c6h 2.250 7h -69.375 47h -45.375 87h -21.375 c7h 2.625 8h -69.000 48h -45.000 88h -21.000 c8h 3.000 9h -68.625 49h -44.625 89h -20.625 c9h 3.375 ah -68.250 4ah -44.250 8ah -20.250 cah 3.750 bh -67.875 4bh -43.875 8bh -19.875 cbh 4.125 ch -67.500 4ch -43.500 8ch -19.500 cch 4.500 dh -67.125 4dh -43.125 8dh -19.125 cdh 4.875 eh -66.750 4eh -42.750 8eh -18.750 ceh 5.250 fh -66.375 4fh -42.375 8fh -18.375 cfh 5.625 10h -66.000 50h -42.000 90h -18.000 d0h 6.000 11h -65.625 51h -41.625 91h -17.625 d1h 6.375 12h -65.250 52h -41.250 92h -17.250 d2h 6.750 13h -64.875 53h -40.875 93h -16.875 d3h 7.125 14h -64.500 54h -40.500 94h -16.500 d4h 7.500 15h -64.125 55h -40.125 95h -16.125 d5h 7.875 16h -63.750 56h -39.750 96h -15.750 d6h 8.250 17h -63.375 57h -39.375 97h -15.375 d7h 8.625 18h -63.000 58h -39.000 98h -15.000 d8h 9.000 19h -62.625 59h -38.625 99h -14.625 d9h 9.375 1ah -62.250 5ah -38.250 9ah -14.250 dah 9.750 1bh -61.875 5bh -37.875 9bh -13.875 dbh 10.125 1ch -61.500 5ch -37.500 9ch -13.500 dch 10.500 1dh -61.125 5dh -37.125 9dh -13.125 ddh 10.875 1eh -60.750 5eh -36.750 9eh -12.750 deh 11.250 1fh -60.375 5fh -36.375 9fh -12.375 dfh 11.625 20h -60.000 60h -36.000 a0h -12.000 e0h 12.000 21h -59.625 61h -35.625 a1h -11.625 e1h 12.375 22h -59.250 62h -35.250 a2h -11.250 e2h 12.750 23h -58.875 63h -34.875 a3h -10.875 e3h 13.125 24h -58.500 64h -34.500 a4h -10.500 e4h 13.500 25h -58.125 65h -34.125 a5h -10.125 e5h 13.875 26h -57.750 66h -33.750 a6h -9.750 e6h 14.250 27h -57.375 67h -33.375 a7h -9.375 e7h 14.625 28h -57.000 68h -33.000 a8h -9.000 e8h 15.000 29h -56.625 69h -32.625 a9h -8.625 e9h 15.375 2ah -56.250 6ah -32.250 aah -8.250 eah 15.750 2bh -55.875 6bh -31.875 abh -7.875 ebh 16.125 2ch -55.500 6ch -31.500 ach -7.500 ech 16.500 2dh -55.125 6dh -31.125 adh -7.125 edh 16.875 2eh -54.750 6eh -30.750 aeh -6.750 eeh 17.250 2fh -54.375 6fh -30.375 afh -6.375 efh 17.625 30h -54.000 70h -30.000 b0h -6.000 f0h 17.625 31h -53.625 71h -29.625 b1h -5.625 f1h 17.625 32h -53.250 72h -29.250 b2h -5.250 f2h 17.625 33h -52.875 73h -28.875 b3h -4.875 f3h 17.625 34h -52.500 74h -28.500 b4h -4.500 f4h 17.625 35h -52.125 75h -28.125 b5h -4.125 f5h 17.625 36h -51.750 76h -27.750 b6h -3.750 f6h 17.625 37h -51.375 77h -27.375 b7h -3.375 f7h 17.625 38h -51.000 78h -27.000 b8h -3.000 f8h 17.625 39h -50.625 79h -26.625 b9h -2.625 f9h 17.625 3ah -50.250 7ah -26.250 bah -2.250 fah 17.625 3bh -49.875 7bh -25.875 bbh -1.875 fbh 17.625 3ch -49.500 7ch -25.500 bch -1.500 fch 17.625 3dh -49.125 7dh -25.125 bdh -1.125 fdh 17.625 3eh -48.750 7eh -24.750 beh -0.750 feh 17.625 3fh -48.375 7fh -24.375 bfh -0.375 ffh 17.625 table 12 adc digital volume range
production data WM8903 w pd, rev 4.5, june 2012 45 high-pass filter (hpf) a digital high-pass filter is applied by default to t he adc path to remove dc offsets. this filter can also be programmed to remove low frequency noi se in handheld applications (e.g. wind noise, handling noise or mechanical vibration). this f ilter is controlled using the adc_hpf_ena and adc_hpf_cut register bits (see table 13). in hi-fi mode the high pass filter is optimised for removing dc offsets without degrading the bass response and has a cut-off frequenc y of 3.7hz at fs=44.1khz. in voice mode the high pass filter is optimised for voice communication and it is recommended to program the cut-off frequency below 300hz (e.g. adc_hpf_cut=11 at fs=8khz or adc_hpf_cut=10 at fs=16khz). register address bit label default description r38 (26h) adc digital 0 6:5 adc_hpf_cut [1:0] 00 adc digital high pass filter cut-off frequency (fc) 00 = hi-fi mode (fc=4hz at fs=48khz) 01 = voice mode 1 (fc=127hz at fs=16khz) 10 = voice mode 2 (fc=130hz at fs=8khz) 11 = voice mode 3 (fc=267hz at fs=8khz) (note: fc scales with sample rate fs. see table 14 for cut-off frequencies at all supported sample rates) 4 adc_hpf_ena 1 adc digital high pass filter enable 0 = disabled 1 = enabled table 13 adc high-pass filter control registers sample rate (khz) value of adc_hpf_cut bits 00 01 10 11 cut-off frequency (hz) 8.000 0.7 64 130 267 11.025 0.9 88 178 367 16.000 1.3 127 258 532 22.050 1.9 175 354 733 24.000 2.0 190 386 798 32.000 2.7 253 514 1063 44.100 3.7 348 707 1464 48.000 4.0 379 770 1594 88.200 7.4 696 1414 2928 96.000 8.0 758 1540 3188 table 14 adc high-pass filter cut-off frequencies the high pass filter characteristics are shown in ?digital filter char acteristics? section.
WM8903 production data w pd, rev 4.5, june 2012 46 adc oversampling ratio (osr) the adc oversampling rate is programmable to allow power consumption versus audio performance trade-offs. the default oversampling rate is high for best performance; using the lower osr setting reduces adc power consumption. register address bit label default description r10 (0ah) analogue adc 0 0 adc_osr128 1 adc oversampling ratio 0 = low power (64 x fs) 1 = high performance (128 x fs) note that the low power options is not supported when clk_sys_mode=10 table 15 adc oversampling ratio note that the low power (64 x fs) oversampli ng option is not supported when clk_sys_mode=10 (see ?clocking and sample rates?, table 62). dynamic range control (drc) the dynamic range controller (drc) is a circuit wh ich can be enabled in the digital data path of the adc. its function is to adjust t he signal gain in conditions where the input amplitude is unknown or varies over a wide range, e.g. when recording from microphones built into a handheld system. the drc can apply compression and automatic level control to the signal path. it incorporates ?anti-clip? and ?quick release? features for hand ling transients in order to improv e intelligibility in the presence of loud impulsive noises. the drc is enabled as shown in table 16. register address bit label default description r40 (28h) drc 0 15 drc_ena 0 drc enable 1 = enabled 0 = disabled table 16 drc enable compression/limiting capabilities the drc supports two different compression regions, specified by r0 and r1, separated by a ?knee? at input amplitude t. for signals above the knee, the compression slope r0 applies; for signals below the knee, the compression slope r1 applies. the overall drc compression characteristic in ?steady state? (i.e. where the input amplitude is near- constant) is illustrated in figure 30.
production data WM8903 w pd, rev 4.5, june 2012 47 drc output amplitude (db) figure 30 drc compression characteristic the slope of r0 and r1 are determined by register fields drc_r0_slope_comp and drc_r1_slope_comp respectively. a slope of 1 indi cates constant gain in this region. a slope less than 1 represents compression (i.e. a change in input amplitude produces only a smaller change in output amplitude). a slope of 0 indicates that the target output amplitude is the same across a range of input amplitudes; this is infinite compression. the ?knee? in figure 30 is represented by t and y, which are determined by register fields drc_thresh_comp and drc_amp_comp respectively. parameter y0, the output level for a 0db input, is not specified directly, but can be calculated from the other parameters, using the equation y0 = yt ? (t * r0) the drc compression parameters are defined in table 17.
WM8903 production data w pd, rev 4.5, june 2012 48 register address bit label default description r42 (2ah) drc 2 5:3 drc_r0_slop e_comp [2:0] 100 compressor slope r0 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 1/16 101 = 0 110 = reserved 111 = reserved 2:0 drc_r1_slop e_comp [2:0] 000 compressor slope r1 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 0 101 = reserved 11x = reserved r43 (2bh) drc 3 10:5 drc_thresh_ comp [5:0] 000000 compressor threshold t (db) 000000 = 0db 000001 = -0.75db 000010 = -1.5db ? (-0.75db steps) 111100 = -45db 111101 = reserved 11111x = reserved 4:0 drc_amp_co mp [4:0] 00000 compressor amplitude at threshold yt (db) 00000 = 0db 00001 = -0.75db 00010 = -1.5db ? (-0.75db steps) 11110 = -22.5db 11111 = reserved table 17 drc compression control gain limits the minimum and maximum gain applied by the drc is set by register fields drc_mingain and drc_maxgain. these limits can be used to alter t he drc response from that illustrated in figure 30. if the range between maximum and minimum gain is reduced, then the extent of the dynamic range control is reduced. the maximum gain pr events quiet signals (or silence) from being excessively amplified.
production data WM8903 w pd, rev 4.5, june 2012 49 register address bit label default description r41(29h) drc 1 3:2 drc_mingain [1:0] 00 minimum gain the drc can use to attenuate audio signals 00 = 0db (default) 01 = -6db 10 = -12db 11 = -18db 1:0 drc_maxgain [1:0] 01 maximum gain the drc can use to boost audio signals 00 = 12db 01 = 18db (default) 10 = 24db 11 = 36db table 18 drc gain limits dynamic characteristics the dynamic behaviour determines how quickly t he drc responds to changing signal levels. note that the drc responds to the average (rms) signal amplitude over a period of time. the drc_attack_rate determines how quickl y the drc gain decreases when the signal amplitude is high. the drc_decay_rate deter mines how quickly the drc gain increases when the signal amplitude is low. these register fields are described in table 19. note that the register defaults are suitable for general purpose microphone use. register address bit label default description r41 (29h) drc 1 15:12 drc_attack_ rate [3:0] 0011 gain attack rate (seconds/6db) 0000 = reserved 0001 = 182s 0010 = 363s 0011 = 726s (default) 0100 = 1.45ms 0101 = 2.9ms 0110 = 5.8ms 0111 = 11.6ms 1000 = 23.2ms 1001 = 46.4ms 1010 = 92.8ms 1011-1111 = reserved 11:8 drc_decay_r ate [3:0] 0010 gain decay rate (seconds/6db) 0000 = 186ms 0001 = 372ms 0010 = 743ms (default) 0011 = 1.49s 0100 = 2.97s 0101 = 5.94s 0110 = 11.89s 0111 = 23.78s 1000 = 47.56s 1001-1111 = reserved table 19 drc attack and decay rates
WM8903 production data w pd, rev 4.5, june 2012 50 note: for detailed information about drc attack and decay rates, please see wolfson application note wan0247. anti-clip control the drc includes an anti-clip feature to avoid si gnal clipping when the input amplitude rises very quickly. this feature uses a feed- forward technique for early detection of a rising signal level. signal clipping is avoided by dynamically increasing the gain attack rate when required. the anti-clip feature is enabled using the drc_anticlip_ena bit. note that the feed-forward processing increases the latency in the input signal path. for low-latency applications (e.g. telephony), it may be desirable to reduce the delay, although this will also reduce the effectiveness of the anti-clip feature. t he latency is determined by the drc_ff_delay bit. if necessary, the latency can be minimised by disabling the anti-clip feature altogether. the drc anti-clip control bits are described in table 20. register address bit label default description r40 (28h) drc 0 5 drc_ff_delay 1 feed-forward delay for anti-clip feature 0 = 5 samples 1 = 9 samples time delay can be calculated as 5/f s or 9/ f s , where f s is the sample rate. 1 drc_anticlip_ ena 1 anti-clip enable 0 = disabled 1 = enabled table 20 drc anti-clip control note that the anti-clip feature operates entirely in the digital domain, i.e. after the adc. it cannot be used to prevent signal clipping in the analogue domain (e.g. in the input pgas or adcs), nor in the source signal. analogue clipping can only be prevented by reduci ng the analogue signal gain or by adjusting the source signal. quick release control the drc includes a quick-release feature to handle s hort transient peaks that are not related to the intended source signal. for example, in handhel d microphone recording, transient signal peaks sometimes occur due to user handling, key pre sses or accidental tapping against the microphone. the quick release feature ensures that these transients do not cause the intended signal to be masked by the longer time constants of drc_decay_rate. the quick-release feature is enabled by setting t he drc_qr_ena bit. when this bit is enabled, the drc measures the crest factor (peak to rms ratio) of the input signal. a high crest factor is indicative of a transient peak that may not be related to t he intended source signal. if the crest factor exceeds the level set by drc_thresh_qr, then the normal decay rate (drc_decay_rate) is ignored and a faster decay rate (drc_rate_qr) is used instead. the drc quick-release control bi ts are described in table 21.
production data WM8903 w pd, rev 4.5, june 2012 51 register address bit label default description r40 (28h) drc 0 2 drc_qr_ena 1 quick release enable 0 = disabled 1 = enabled r41 (29h) drc 1 7:6 drc_thresh_ qr [1:0] 01 quick release crest factor threshold 00 = 12db 01 = 18db (default) 10 = 24db 11 = 30db 5:4 drc_rate_qr [1:0] 00 quick release decay rate (seconds/6db) 00 = 0.725ms (default) 01 = 1.45ms 10 = 5.8ms 11 = reserved table 21 drc quick-release control gain smoothing the drc includes a gain smoothing filter in order to prevent gain ripples. a programmable level of hysteresis is also used to control the drc gain. this improves the handling of very low frequency input signals whose period is close to the drc a ttack/decay time. drc gain smoothing is enabled by default and it is recommended to us e the default register settings. the extent of the gain smoothing filter may be adjus ted or disabled using the control fields described in table 22. register address bit label default description r40 (28h) drc 0 12:11 drc_thresh_ hyst [1:0] 01 gain smoothing hysteresis threshold 00 = low 01 = medium (recommended) 10 = high 11 = reserved 3 drc_smooth_ ena 1 gain smoothing enable 0 = disabled 1 = enabled 0 drc_hyst_en a 1 gain smoothing hysteresis enable 0 = disabled 1 = enabled table 22 drc gain smoothing
WM8903 production data w pd, rev 4.5, june 2012 52 initialisation when the drc is initialised, the gain is set to the level determined by the drc_startup_gain register field. the default setting is 0db, but values from -18db to +36db are available, as described in table 23. register address bit label default description r40 (28h) drc 0 10:6 drc_startup_ gain [4:0] 00110 initial gain at drc startup 00000 = -18db 00001 = -15db 00010 = -12db 00011 = -9db 00100 = -6db 00101 = -3db 00110 = 0db (default) 00111 = 3db 01000 = 6db 01001 = 9db 01010 = 12db 01011 = 15db 01100 = 18db 01101 = 21db 01110 = 24db 01111 = 27db 10000 = 30db 10001 = 33db 10010 = 36db 10011 to 11111 = reserved table 23 drc initialisation
production data WM8903 w pd, rev 4.5, june 2012 53 digital mixing the adc and dac data can be combined in various ways to support a range of different usage modes. data from either of the two adcs can be routed to either the left or the right channel of the digital audio interface. in addition, data from either of the digital audio interface channels can be routed to either the left or the right dac. see ?digital audio interface? for more information on the audio interface. the WM8903 provides a dynamic range control ( drc) feature, which can apply compression and gain adjustment in the digital domain to the adc si gnal path. this is effective in controlling signal levels under conditions where input amplitude is unknown or varies over a wide range. the dacs can be configured as a mono mix of the two audio channel s. digital sidetone from the adcs can also be selectively mixed into the dac output path. digital mixing paths figure 31 shows the digital mixing paths available in the WM8903 digital core. figure 31 digital mixing paths
WM8903 production data w pd, rev 4.5, june 2012 54 the polarity of each adc output signal c an be changed under software control using the adcl_datinv and adcr_datinv register bits . the aifadcl_src and aifadcr_src register bits may be used to select which adc is used for the left and right digital audio interface data. these register bits are described in table 24. register address bit label default description r24 (18h) audio interface 0 7 aifadcl_src 0 left digital audio channel source 0 = left adc data is output on left channel 1 = right adc data is output on left channel 6 aifadcr_src 1 right digital audio channel source 0 = left adc data is output on right channel 1 = right adc data is output on right channel r38 (26h) adc digital 0 1 adcl_datinv 0 left adc invert 0 = left adc output not inverted 1 = left adc output inverted 0 adcr_datinv 0 right adc invert 0 = right adc output not inverted 1 = right adc output inverted table 24 adc routing and control the input data source for each dac can be changed under software control using register bits dacl_src and dacr_src. the polarity of each dac input may also be modified using register bits dacl_datinv and dacr_datinv. these r egister bits are described in table 25. register address bit label default description r24 (18h) audio interface 0 12 dacl_datinv 0 left dac invert 0 = left dac output not inverted 1 = left dac output inverted 11 dacr_datinv 0 right dac invert 0 = right dac output not inverted 1 = right dac output inverted 5 aifdacl_src 0 left dac data source select 0 = left dac outputs left channel data 1 = left dac outputs right channel data 4 aifdacr_src 1 right dac data source select 0 = right dac outputs left channel data 1 = right dac outputs right channel data table 25 dac routing and control dac interface volume boost a digital gain function is availabl e at the audio interface to boost the dac volume when a small signal is received on dacdat. this is c ontrolled using register bits dac_ boost [1:0]. to prevent clipping at the dac input, this function should not be used when the boosted dac data is expected to be greater than 0dbfs.
production data WM8903 w pd, rev 4.5, june 2012 55 the digital interface volume is controlled as shown in table 26. register address bit label default description r24 (18h) audio interface 0 10:9 dac_boost [1:0] 00 dac input volume boost 00 = 0db 01 = +6db (input data must not exceed -6dbfs) 10 = +12db (input data must not exceed -12dbfs) 11 = +18db (input data must not exceed -18dbfs) table 26 dac interface volume boost digital sidetone digital sidetone mixing (from adc output into da c input) is available when adcs and dacs are operating at the same sample rate. digital data from either left or right adc can be mixed with the audio interface data on the left and right dac c hannels. sidetone data is taken from the adc high-pass filter output, to reduce low frequency noise in the sidetone (e.g. wind noise or mechanical vibration). when using the digital sidetone, it is recomm ended that the adcs are enabled before un-muting the dacs to prevent pop noise. the dac volumes and sidetone volumes should be set to an appropriate level to avoid clipping at the dac input. when digital sidetone is used, it is recommended that the charge pump operates in register control mode only (cp_dyn_pwr = 0). see ?charge pump? for details. the digital sidetone is contro lled as shown in table 27. register address bit label default description r32 (20h) dac digital 0 11:8 adcl_dac_sv ol [3:0] 0000 left digital sidetone volume 0000 = -36db 0001 = -33db (? 3db steps) 1011 = -3db 11xx = 0db (see table 28 for volume range) 7:4 adcr_dac_sv ol [3:0] 0000 right digital sidetone volume 0000 = -36db 0001 = -33db (? 3db steps) 1011 = -3db 11xx = 0db (see table 28 for volume range) 3:2 adc_to_dacl [1:0] 00 left dac digital sidetone source 00 = no sidetone 01 = left adc 10 = right adc 11 = reserved 1:0 adc_to_dacr [1:0] 00 right dac digital sidetone source 00 = no sidetone 01 = left adc 10 = right adc 11 = reserved table 27 digital sidetone control
WM8903 production data w pd, rev 4.5, june 2012 56 the digital sidetone volume settings are shown in table 28. adcl_dac_svol or adcr_dac_svol sidetone volume 0000 -36 0001 -33 0010 -30 0011 -27 0100 -24 0101 -21 0110 -18 0111 -15 1000 -12 1001 -9 1010 -6 1011 -3 1100 0 1101 0 1110 0 1111 0 table 28 digital sidetone volume digital-to-analogue converter (dac) the WM8903 dacs receive digital input data from the dacdat pin and via the digital sidetone path (see ?digital mixing? section). t he digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. the bitstream data enters two multi-bit, sigma-delta dacs, which convert them to high quality analogue audio signals. the wolfson smartdac? architecture offers reduced power consumption, whilst also delivering a reduction in high frequency noise and sensitivity to clock jitter. it also us es a dynamic element ma tching technique for high linearity and low distortion. the analogue outputs from the dacs can then be mi xed with other analogue inputs before being sent to the analogue output pins (see ?output signal path?). the dacs are enabled by the dacl_e na and dacr_ena register bits. register address bit label default description r18 (12h) power management 6 3 dacl_ena 0 left dac enable 0 = dac disabled 1 = dac enabled 2 dacr_ena 0 right dac enable 0 = dac disabled 1 = dac enabled table 29 dac enable control
production data WM8903 w pd, rev 4.5, june 2012 57 dac digital volume control the output level of each dac can be controlled di gitally over a range from -71.625db to 0db in 0.375db steps. the level of attenuation for an eight-bit code is detailed in table 31. the dac_vu bit controls the loading of digital volu me control data. when dac_vu is set to 0, the dacl_vol or dacr_vol control data is loaded into the respective control register, but does not actually change the digital gain setting. both left and right gain settings are updated when a 1 is written to dac_vu. this makes it possible to update the gain of both channels simultaneously. register address bit label default description r30 (1eh) dac digital volume left 8 dacvu n/a dac volume update writing a 1 to this bit causes left and right dac volume to be updated simultaneously (write-only register) 7:0 dacl_vol [7:0] 1100_0000 (0db) left dac digital volume 00h = mute 01h = -71.625db 02h = -71.250db ? (0.375db steps) c0h = 0db ? (0.375db steps) efh to ffh = +17.625db (see table 31 for volume range) r31 (1fh) dac digital volume right 8 dacvu n/a dac volume update writing a 1 to this bit causes left and right dac volume to be updated simultaneously (write-only register) 7:0 dacr_vol [7:0] 1100_0000 (0db) right dac digital volume 00h = mute 01h = -71.625db 02h = -71.250db ? (0.375db steps) c0h = 0db ? (0.375db steps) efh to ffh = +17.625db (see table 31 for volume range) table 30 dac digital volume control
WM8903 production data w pd, rev 4.5, june 2012 58 dacl_vol or dacr_vol volume (db) dacl_vol or dacr_vol volume (db) dacl_vol or dacr_vol volume (db) dacl_vol or dacr_vol volume (db) 0h mute 40h -48.000 80h -24.000 c0h 0.000 1h -71.625 41h -47.625 81h -23.625 c1h 0.000 2h -71.250 42h -47.250 82h -23.250 c2h 0.000 3h -70.875 43h -46.875 83h -22.875 c3h 0.000 4h -70.500 44h -46.500 84h -22.500 c4h 0.000 5h -70.125 45h -46.125 85h -22.125 c5h 0.000 6h -69.750 46h -45.750 86h -21.750 c6h 0.000 7h -69.375 47h -45.375 87h -21.375 c7h 0.000 8h -69.000 48h -45.000 88h -21.000 c8h 0.000 9h -68.625 49h -44.625 89h -20.625 c9h 0.000 ah -68.250 4ah -44.250 8ah -20.250 cah 0.000 bh -67.875 4bh -43.875 8bh -19.875 cbh 0.000 ch -67.500 4ch -43.500 8ch -19.500 cch 0.000 dh -67.125 4dh -43.125 8dh -19.125 cdh 0.000 eh -66.750 4eh -42.750 8eh -18.750 ceh 0.000 fh -66.375 4fh -42.375 8fh -18.375 cfh 0.000 10h -66.000 50h -42.000 90h -18.000 d0h 0.000 11h -65.625 51h -41.625 91h -17.625 d1h 0.000 12h -65.250 52h -41.250 92h -17.250 d2h 0.000 13h -64.875 53h -40.875 93h -16.875 d3h 0.000 14h -64.500 54h -40.500 94h -16.500 d4h 0.000 15h -64.125 55h -40.125 95h -16.125 d5h 0.000 16h -63.750 56h -39.750 96h -15.750 d6h 0.000 17h -63.375 57h -39.375 97h -15.375 d7h 0.000 18h -63.000 58h -39.000 98h -15.000 d8h 0.000 19h -62.625 59h -38.625 99h -14.625 d9h 0.000 1ah -62.250 5ah -38.250 9ah -14.250 dah 0.000 1bh -61.875 5bh -37.875 9bh -13.875 dbh 0.000 1ch -61.500 5ch -37.500 9ch -13.500 dch 0.000 1dh -61.125 5dh -37.125 9dh -13.125 ddh 0.000 1eh -60.750 5eh -36.750 9eh -12.750 deh 0.000 1fh -60.375 5fh -36.375 9fh -12.375 dfh 0.000 20h -60.000 60h -36.000 a0h -12.000 e0h 0.000 21h -59.625 61h -35.625 a1h -11.625 e1h 0.000 22h -59.250 62h -35.250 a2h -11.250 e2h 0.000 23h -58.875 63h -34.875 a3h -10.875 e3h 0.000 24h -58.500 64h -34.500 a4h -10.500 e4h 0.000 25h -58.125 65h -34.125 a5h -10.125 e5h 0.000 26h -57.750 66h -33.750 a6h -9.750 e6h 0.000 27h -57.375 67h -33.375 a7h -9.375 e7h 0.000 28h -57.000 68h -33.000 a8h -9.000 e8h 0.000 29h -56.625 69h -32.625 a9h -8.625 e9h 0.000 2ah -56.250 6ah -32.250 aah -8.250 eah 0.000 2bh -55.875 6bh -31.875 abh -7.875 ebh 0.000 2ch -55.500 6ch -31.500 ach -7.500 ech 0.000 2dh -55.125 6dh -31.125 adh -7.125 edh 0.000 2eh -54.750 6eh -30.750 aeh -6.750 eeh 0.000 2fh -54.375 6fh -30.375 afh -6.375 efh 0.000 30h -54.000 70h -30.000 b0h -6.000 f0h 0.000 31h -53.625 71h -29.625 b1h -5.625 f1h 0.000 32h -53.250 72h -29.250 b2h -5.250 f2h 0.000 33h -52.875 73h -28.875 b3h -4.875 f3h 0.000 34h -52.500 74h -28.500 b4h -4.500 f4h 0.000 35h -52.125 75h -28.125 b5h -4.125 f5h 0.000 36h -51.750 76h -27.750 b6h -3.750 f6h 0.000 37h -51.375 77h -27.375 b7h -3.375 f7h 0.000 38h -51.000 78h -27.000 b8h -3.000 f8h 0.000 39h -50.625 79h -26.625 b9h -2.625 f9h 0.000 3ah -50.250 7ah -26.250 bah -2.250 fah 0.000 3bh -49.875 7bh -25.875 bbh -1.875 fbh 0.000 3ch -49.500 7ch -25.500 bch -1.500 fch 0.000 3dh -49.125 7dh -25.125 bdh -1.125 fdh 0.000 3eh -48.750 7eh -24.750 beh -0.750 feh 0.000 3fh -48.375 7fh -24.375 bfh -0.375 ffh 0.000 table 31 dac digital volume range
production data WM8903 w pd, rev 4.5, june 2012 59 dac soft mute and soft un-mute the WM8903 has a soft mute function. when enabled, this gradually attenuates the volume of the dac output. when soft mute is disabled, the gain will either gradually ramp back up to the digital gain setting, or return instantly to the digital gai n setting, depending on the dac_mutemode register bit. the dac is not muted by default (dac_mute = 0). to mute the dac, this function must be enabled by setting dac_mute to 1. soft mute mode would typically be enabled (dac_m utemode = 1) when using dac_mute during playback of audio data so that when dac_mute is subsequently disabled, the sudden volume increase will not create pop noise by jumping immediat ely to the previous volume level (e.g. resuming playback after pausing during a track). soft mute mode would typically be disabled (dac_mutemode = 0) when un-muting at the start of a music file, in order that the first part of the tr ack is not attenuated (e.g. when starting playback of a new track, or resuming playback after pausing between tracks). dac muting and un-muting using volume control bits dacl_vol and dacr_vol. dac muting and un-muting using the dac_mute bit. if soft mute mode is not enabled (dac_mutemode = 0): setting the dac_mute bit causes the volume to ramp down at a rate controlled by dac_muterate. clearing the dac_mute bit causes the volume to return to the un-muted level immediately. dac muting and un-muting using the dac_mute bit. if soft mute mode is enabled (dac_mutemode = 1): setting the dac_mute bit causes the volume to ramp down. clearing the dac_mute bit causes the volume to ramp up to the un-muted level at a rate controlled by dac_muterate. figure 32 dac mute control the volume ramp rate during soft mute and un-mute is controlled by the dac_muterate bit. ramp rates of fs/32 and fs/2 can be selected, as shown in table 32. the ramp rate determines the rate at which the volume is increased or decreased. the actual ramp time depends on the extent of the difference between the muted and un-muted volume settings.
WM8903 production data w pd, rev 4.5, june 2012 60 register address bit label default description r33 (21h) dac digital 1 10 dac_mutera te 0 dac soft mute ramp rate 0 = fast ramp (fs/2, maximum ramp time is 10.7ms at fs=48k) 1 = slow ramp (fs/32, maximum ramp time is 171ms at fs=48k) 9 dac_mutem ode 0 dac soft mute mode 0 = disabling soft-mute (dac_mute=0) will cause the dac volume to change immediately to dacl_vol and dacr_vol settings 1 = disabling soft-mute (dac_mute=0) will cause the dac volume to ramp up gradually to the dacl_vol and dacr_vol settings 3 dac_mute 0 dac soft mute control 0 = dac un-mute 1 = dac mute table 32 dac soft-mute control dac mono mix a dac digital mono-mix mode can be enabled using t he dac_mono register bit. this mono mix will be output on whichever dac is enabled. to prevent clipping, a -6db attenuation is automatically applied to the mono mix. the mono mix is only supported when one or other da c is disabled. when the mono mix is selected, then the mono mix is output on the enabled dac only; there is no output from the disabled dac. if dacl_ena and dacr_ena are both set, then stereo operation applies. register address bit label default description r33 (21h) dac digital 1 12 dac_mono 0 dac mono mix 0 = stereo 1 = mono (mono mix output on enabled dac) table 33 dac mono mix dac de-emphasis digital de-emphasis can be applied to the dac pl ayback data (e.g. when the data comes from a cd with pre-emphasis used in the recording). de-emphas is filtering is available for sample rates of 48khz, 44.1khz and 32khz. see ?digit al filter characteristics? fo r details of de-emphasis filter characteristics. register address bit label default description r33 (21h) dac digital 1 2:1 deemph [1:0] 00 dac de-emphasis control 00 = no de-emphasis 01 = 32khz sample rate 10 = 44.1khz sample rate 11 = 48khz sample rate table 34 dac de-emphasis control
production data WM8903 w pd, rev 4.5, june 2012 61 dac sloping stopband filter two dac filter types are available, selected by the register bit dac_sb_filt. when operating at sample rates <= 24khz (e.g. during voice comm unication) it is recommended that the sloping stopband filter type is selected (dac_sb_filt=1) to reduce out-of-band noise which can be audible at low dac sample rates. see ?digital filter characte ristics? for details of dac filter characteristics. register address bit label default description r33 (21h) dac digital 1 11 dac_sb_filt 0 selects dac filter characteristics 0 = normal mode 1 = sloping stopband mode (recommended when fs ??? 24khz ? table 35 dac sloping stopband filter dac bias control the analogue circuits within the dac use the ma ster bias current (see ?reference voltages and master bias?). the dac bias currents c an also be reduced using the dacbias_sel and dacvmid_sel fields as described in table 36. these can be used to reduc e power consumption, but may have a marginal impact on audi o performance in some usage modes. the dac bias currents can be increased using the dac_bias_boost field. setting this bit doubles the bias level of dacbias_sel and dacvmid_bi as_sel. this offers a performance improvement, but also an increase in power consumption. note that the increased dac vmid buffer bias is unlikely to give better performance; when dac_bias_boost is set, it is recommended to set dacvmid_bias_sel = 01 in order to restore the normal dac vmid buffer bias level. register address bit label default description r8 (08h) analogue dac 0 5 dac_bias_boo st 0 dac bias boost 0 = disable 1 = enable when dac bias boost is enabled, the bias selected by dacbias_sel and dacvmid_bias_sel are both doubled. 4:3 dacbias_sel 00 dac bias current select 00 = normal bias 01 = normal bias x 0.5 10 = normal bias x 0.66 11 = normal bias x 0.75 2:1 dacvmid_bias_ sel 00 dac vmid buffer bias select 00 = normal bias 01 = normal bias x 0.5 10 = normal bias x 0.66 11 = normal bias x 0.75 table 36 dac bias control
WM8903 production data w pd, rev 4.5, june 2012 62 dac oversampling ratio (osr) the dac oversampling rate is programmable to allow power consumption versus audio performance trade-offs. the default oversampling rate is low for reduced power consumpt ion; using the higher osr setting improves the dac signal-to-noise performance. register address bit label default description r33 (21h) dac digital 1 0 dac_osr 0 dac oversampling control 0 = low power (normal oversample) 1 = high performance (double rate) table 37 dac oversampling control
production data WM8903 w pd, rev 4.5, june 2012 63 output signal path the outputs hpoutl and lineoutl are derived from the left mixer, whilst the hpoutr and lineoutr are derived from the right mixer. t hese mixers allow the stereo dac and stereo bypass signals to be mixed together for the headphone and line outputs. a feedback path for common mode noise rejection is provided at hpgnd and linegnd for the headphone and line outputs respectively. this pi n must be connected to ground for normal operation. the outputs lop/lon and rop/ron ar e differential line outputs derived from the left speaker mixer and right speaker mixer respectively. each analogue output can be separately enabled; independent volume control is also provided for each output. the output signal paths and associated cont rol registers are illustrated in figure 33. see ?analogue outputs? for details of the ex ternal connections to these outputs. figure 33 output signal path and control registers
WM8903 production data w pd, rev 4.5, june 2012 64 output signal paths enable the output mixers and drivers can be independently enabled and disabled using the register bits described in table 38. note that the headphone outputs and line outputs are also controlled by fields located within register r90 and r94, which provide suppre ssion of pops & clicks when enabling and disabling these signal paths. these registers are descri bed in the following ?headphone / line output signal paths enable? section. under recommended usage conditions, the pop suppre ssion control bits will be configured by scheduling the default start-up and shut-down s equences as described in the ?control write sequencer? section. in these cases, the user does not need to set the register fields in r13, r14, r15, r90 and r94 directly. register address bit label default description r13 (0dh) power management 1 1 mixoutl_ena 0 left output mixer enable 0 = disabled 1 = enabled 0 mixoutr_ena 0 right output mixer enable 0 = disabled 1 = enabled r14 (0eh) power management 2 1 hpl_pga_ena 0 left headphone output enable 0 = disabled 1 = enabled 0 hpr_pga_ena 0 right headphone output enable 0 = disabled 1 = enabled r15 (0fh) power management 3 1 lineoutl_pga_ ena 0 left line output enable 0 = disabled 1 = enabled 0 lineoutr_pga _ena 0 right line output enable 0 = disabled 1 = enabled r16 (10h) power management 4 1 mixspkl_ena 0 left speaker mixer enable 0 = disabled 1 = enabled 0 mixspkr_ena 0 right speaker mixer enable 0 = disabled 1 = enabled r17 (11h) power management 5 1 spkl_ena 0 left speaker output enable 0 = disabled 1 = enabled 0 spkr_ena 0 right speaker output enable 0 = disabled 1 = enabled table 38 output signal paths enable to enable the output pgas and mixers, the reference voltage vmid and the bias current must also be enabled. see ?reference voltages and master bias? fo r details of the associated controls vmid_res and bias_ena.
production data WM8903 w pd, rev 4.5, june 2012 65 headphone / line output signal paths enable the headphone / line output paths can be actively di scharged to agnd through internal resistors if desired. this is desirable at start-up in order to achieve a known output stage condition prior to enabling the vmid reference voltage. this is also desirable in shutdown to prevent the external connections from being affected by the inter nal circuits. the ground-referenced headphone outputs and line outputs are shorted to agnd by default; the s hort circuit is removed on each of these paths by setting the applicable fields hpl_rmv_sho rt, hpr_rmv_short, lineoutl_rmv_short or lineoutr_rmv_short. the ground-referenced headphone output and line output drivers are designed to suppress pops and clicks when enabled or disabled. however, it is necessary to control the drivers in accordance with a defined sequence in start-up and shut-down to achieve the pop suppression. it is also necessary to schedule the dc servo offset correct ion at the appropriate point in the sequence (see ?dc servo?). table 39 and table 40 descr ibe the recommended sequences for enabling and disabling these output drivers. sequence headphone enable lineout enable step 1 hpl_ena = 1 hpr_ena = 1 lineoutl_ena = 1 lineoutr_ena = 1 step 2 hpl_ena_dly = 1 hpr_ena_dly = 1 lineoutl_ena_dly = 1 lineoutr_ena_dly = 1 step 3 dc offset correction dc offset correction step 4 hpl_ena_outp = 1 hpr_ena_outp = 1 lineoutl_ena_outp = 1 lineoutr_ena_outp = 1 step 5 hpl_rmv_short = 1 hpr_rmv_short = 1 lineoutl_rmv_short = 1 lineoutr_rmv_short = 1 table 39 headphone / line output enable sequence sequence headphone disable lineout disable step 1 hpl_rmv_short = 0 hpr_rmv_short = 0 lineoutl_rmv_short = 0 lineoutr_rmv_short = 0 step 2 hpl_ena = 0 hpl_ena_dly = 0 hpl_ena_outp = 0 hpr_ena = 0 hpr_ena_dly = 0 hpr_ena_outp = 0 lineoutl_ena = 0 lineoutl_ena_dly = 0 lineoutl_ena_outp = 0 lineoutr_ena = 0 lineoutr_ena_dly = 0 lineoutr_ena_outp = 0 table 40 headphone / line output disable sequence the registers relating to headphone / line output pop suppression control are defined in table 41. register address bit label default description r90 (5ah) analogue hp 0 7 hpl_rmv_shor t 0 removes hpl short 0 = hpl short enabled 1 = hpl short removed for normal operation, this bit should be set as the final step of the hpl enable sequence. 6 hpl_ena_outp 0 enables hpl output stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the dc offset cancellation has been scheduled.
WM8903 production data w pd, rev 4.5, june 2012 66 register address bit label default description 5 hpl_ena_dly 0 enables hpl intermediate stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the output signal path has been configured, and before dc offset cancellation is scheduled. this bit should be set with at least 20us delay after hpl_ena. 4 hpl_ena 0 enables hpl input stage 0 = disabled 1 = enabled for normal operation, this bit should be set as the first step of the hpl enable sequence. 3 hpr_rmv_sho rt 0 removes hpr short 0 = hpr short enabled 1 = hpr short removed for normal operation, this bit should be set as the final step of the hpr enable sequence. 2 hpr_ena_outp 0 enables hpr output stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the dc offset cancellation has been scheduled. 1 hpr_ena_dly 0 enables hpr intermediate stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the output signal path has been configured, and before dc offset cancellation is scheduled. this bit should be set with at least 20us delay after hpr_ena. 0 hpr_ena 0 enables hpr input stage 0 = disabled 1 = enabled for normal operation, this bit should be set as the first step of the hpr enable sequence.
production data WM8903 w pd, rev 4.5, june 2012 67 register address bit label default description r94 (5eh) analogue lineout 0 7 lineoutl_rmv_ short 0 removes lineoutl short 0 = lineoutl short enabled 1 = lineoutl short removed for normal operation, this bit should be set as the final step of the lineoutl enable sequence. 6 lineoutl_ena_ outp 0 enables lineoutl output stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the dc offset cancellation has been scheduled. 5 lineoutl_ena_ dly 0 enables lineoutl intermediate stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the output signal path has been configured, and before dc offset cancellation is scheduled. this bit should be set with at least 20us delay after lineoutl_ena. 4 lineoutl_ena 0 enables lineoutl input stage 0 = disabled 1 = enabled for normal operation, this bit should be set as the first step of the lineoutl enable sequence. 3 lineoutr_rmv _short 0 removes lineoutr short 0 = lineoutr short enabled 1 = lineoutr short removed for normal operation, this bit should be set as the final step of the lineoutr enable sequence. 2 lineoutr_ena_ outp 0 enables lineoutr output stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the dc offset cancellation has been scheduled. 1 lineoutr_ena_ dly 0 enables lineoutr intermediate stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the output signal path has been configured, and before dc offset cancellation is scheduled. this bit should be set with at least 20us delay after lineoutr_ena. 0 lineoutr_ena 0 enables lineoutr input stage 0 = disabled 1 = enabled for normal operation, this bit should be set as the first step of the lineoutr enable sequence. table 41 headphone / line output pop suppression control
WM8903 production data w pd, rev 4.5, june 2012 68 output pga bias control the output pga circuits use the master bias curr ent (see ?reference voltages and master bias?). the output pga bias currents can also be controlled us ing the pga_bias field as described in table 42. selecting a lower bias can be used to reduce power consumption, but may have a marginal impact on audio performance in some usage modes. selecting a higher bias offers a performance improvement, but also an increase in power consumption. register address bit label default description r172 (ach) analogue output bias 0 6:4 pga_bias [2:0] 000 headphone and lineout pga bias control 000 = normal bias 001 = normal bias x 1.5 010 = normal bias x 0.75 011 = normal bias x 0.5 100 = normal bias x 0.33 101 = normal bias 110 = normal bias 111 = normal bias x 2 table 42 output pga bias control output drivers bias control the bias of the headphone and lineout drivers c an be controlled independently of the pga bias. these may be increased or decreased using the outp uts_bias field as described in table 43. this can be used to reduce power consum ption or improve performance. if it is desired to improve the performance of the outputs with the minimum increase in power consumption, then it is recommended to increas e the outputs_bias level and to use the default setting of pga_bias. register address bit label default description r187 (bbh) analogue output bias 2 2:0 outputs_bias [2:0] 000 headphone and lineout output drivers bias control 000 = normal bias 001 = normal bias x 1.5 010 = normal bias x 0.75 011 = normal bias x 0.5 100 = normal bias x 0.33 101 = normal bias 110 = normal bias 111 = normal bias x 2 table 43 output drivers bias control
production data WM8903 w pd, rev 4.5, june 2012 69 output mixer control each of the four output mixers has the same four inputs: ? dac left ? dac right ? bypass left ? bypass right the input signals to the left and right mixers (feeding hpoutl/r and lineoutl/r) are enabled using the register fields descri bed in table 44. these mixers do not provide volume controls on the inputs or outputs. however, input signals can be attenuated at source using the control fields lin_vol, rin_vol, dacl_vol and dacr_vol. register address bit label default description r50 (32h) analogue left mix 0 3 dacl_to_mixo utl 1 left dac to left output mixer enable 0 = disabled 1 = enabled 2 dacr_to_mixo utl 0 right dac to left output mixer enable 0 = disabled 1 = enabled 1 bypassl_to_mi xoutl 0 left analogue input to left output mixer enable 0 = disabled 1 = enabled 0 bypassr_to_m ixoutl 0 right analogue input to left output mixer enable 0 = disabled 1 = enabled r51 (33h) analogue right mix 0 3 dacl_to_mixo utr 0 left dac to right output mixer enable 0 = disabled 1 = enabled 2 dacr_to_mixo utr 1 right dac to right output mixer enable 0 = disabled 1 = enabled 1 bypassl_to_mi xoutr 0 left analogue input to right output mixer enable 0 = disabled 1 = enabled 0 bypassr_to_m ixoutr 0 right analogue input to right output mixer enable 0 = disabled 1 = enabled table 44 headphone and line output mixer control
WM8903 production data w pd, rev 4.5, june 2012 70 the input signals to the speaker mixers are enabled and controlled usi ng the register fields described in table 45. these mixers provide a selectabl e 0db or -6db volume control on each input. the input signals may also be controlled at source using the cont rol fields lin_vol, rin_vol, dacl_vol and dacr_vol, but it should be noted that adjusting thes e fields would also affect the other output mixers. register address bit label default description r52 (34h) analogue spk mix left 0 3 dacl_to_mixsp kl 0 left dac to left spkr mixer enable 0 = disabled 1 = enabled 2 dacr_to_mixs pkl 0 right dac to left spkr mixer enable 0 = disabled 1 = enabled 1 bypassl_to_mi xspkl 0 left analogue input to left spkr mixer enable 0 = disabled 1 = enabled 0 bypassr_to_mi xspkl 0 right analogue input to left spkr mixer enable 0 = disabled 1 = enabled r53 (35h) analogue spk mix left 1 3 dacl_mixspkl_ vol 0 left dac to left spkr mixer volume control 0 = 0db 1 = -6db 2 dacr_mixspkl_ vol 0 right dac to left spkr mixer volume control 0 = 0db 1 = -6db 1 bypassl_mixsp kl_vol 0 left analogue input to left spkr mixer volume control 0 = 0db 1 = -6db 0 bypassr_mixsp kl_vol 0 right analogue input to left spkr mixer volume control 0 = 0db 1 = -6db r54 (36h) analogue spk mix right 0 3 dacl_to_mixsp kr 0 left dac to right spkr mixer enable 0 = disabled 1 = enabled 2 dacr_to_mixs pkr 0 right dac to right spkr mixer enable 0 = disabled 1 = enabled 1 bypassl_to_mi xspkr 0 left analogue input to right spkr mixer enable 0 = disabled 1 = enabled 0 bypassr_to_mi xspkr 0 right analogue input to right spkr mixer enable 0 = disabled 1 = enabled
production data WM8903 w pd, rev 4.5, june 2012 71 register address bit label default description r55 (37h) analogue spk mix right 1 3 dacl_mixspkr_ vol 0 left dac to right spkr mixer volume control 0 = 0db 1 = -6db 2 dacr_mixspkr _vol 0 right dac to right spkr mixer volume control 0 = 0db 1 = -6db 1 bypassl_mixsp kr_vol 0 left analogue input to right spkr mixer volume control 0 = 0db 1 = -6db 0 bypassr_mixsp kr_vol 0 right analogue input to right spkr mixer volume control 0 = 0db 1 = -6db table 45 speaker mixer control output volume control each analogue output can be independently controll ed. the headphone output control fields are described in table 46. the line output control fields are described in table 47. the differential line output control fields are described in table 48. the output pins are described in more detail in ?analogue outputs?. the volume and mute status of each output can be cont rolled individually using t he bit fields shown in table 46, table 47 and table 48. to prevent ?zipper noise? when a volume adjustment is made, a zero-cross function is provided on all output paths. when this function is enabled, volume updates will not take place until a zero-crossing is detected. in the event of a long period without zero-crossings, a timeout will apply. the timeout must be enabled by setting the to_ena bit, as defined in ?clocking and sample rates?. the volume update bits control the loading of the output driver volume data. for example, when hpoutvu is set to 0, the headphone volume data can be loaded into the respective control register, but will not actually change the gain setting. the left and right headphone volume settings are updated when a 1 is written to hpoutvu. this make s it possible to update the gain of a left/right pair of output paths simultaneously.
WM8903 production data w pd, rev 4.5, june 2012 72 register address bit label default description r57 (39h) analogue out1 left 8 hpl_mute 0 left headphone output mute 0 = un-mute 1 = mute 7 hpoutvu 0 headphone output volume update writing a 1 to this bit will update hpoutl and hpoutr volumes simultaneously. (write-only register) 6 hpoutlzc 0 left headphone output zero cross enable 0 = disabled 1 = enabled 5:0 hpoutl_vol [5:0] 10_1101 left headphone output volume 000000 = -57db 000001 = -56db (? 1db steps) 111001 = 0db (? 1db steps) 111110 = +5db 111111 = +6db r58 (3ah) analogue out1 right 8 hpr_mute 0 right headphone output mute 0 = un-mute 1 = mute 7 hpoutvu 0 headphone output volume update writing a 1 to this bit will update hpoutl and hpoutr volumes simultaneously. (write-only register) 6 hpoutrzc 0 right headphone output zero cross enable 0 = disabled 1 = enabled 5:0 hpoutr_vol [5:0] 10_1101 right headphone output volume 000000 = -57db 000001 = -56db (? 1db steps) 111001 = 0db (? 1db steps) 111110 = +5db 111111 = +6db table 46 volume control for hpoutl and hpoutr
production data WM8903 w pd, rev 4.5, june 2012 73 register address bit label default description r59 (3bh) analogue out2 left 8 lineoutl_mute 0 left line output mute 0 = un-mute 1 = mute 7 lineoutvu 0 line output volume update writing a 1 to this bit will update lineoutl and lineoutr volumes simultaneously. (write-only register) 6 lineoutlzc 0 left line output zero cross enable 0 = disabled 1 = enabled 5:0 lineoutl_vol [5:0] 11_1001 left line output volume 000000 = -57db 000001 = -56db (? 1db steps) 111001 = 0db (? 1db steps) 111110 = +5db 111111 = +6db r60 (3ch) analogue out2 right 8 lineoutr_mut e 0 right line output mute 0 = un-mute 1 = mute 7 lineoutvu 0 line output volume update writing a 1 to this bit will update lineoutl and lineoutr volumes simultaneously. (write-only register) 6 lineoutrzc 0 right line output zero cross enable 0 = disabled 1 = enabled 5:0 lineoutr_vol [5:0] 11_1001 right line output volume 000000 = -57db 000001 = -56db (? 1db steps) 111001 = 0db (? 1db steps) 111110 = +5db 111111 = +6db table 47 volume control for lineoutl and lineoutr
WM8903 production data w pd, rev 4.5, june 2012 74 register address bit label default description r62 (3eh) analogue out3 left 8 spkl_mute 1 left speaker output mute 0 = un-mute 1 = mute 7 spkvu 0 speaker output volume update writing a 1 to this bit will update lon/lop and ron/rop volumes simultaneously. (write-only register) 6 spklzc 0 left speaker output zero cross enable 0 = disabled 1 = enabled 5:0 spkl_vol [5:0] 11_1001 left speaker output volume 000000 = -57db 000001 = -56db (? 1db steps) 111001 = 0db (? 1db steps) 111110 = +5db 111111 = +6db r63 (3fh) analogue out3 right 8 spkr_mute 1 right speaker output mute 0 = un-mute 1 = mute 7 spkvu 0 speaker output volume update writing a 1 to this bit will update lon/lop and ron/rop volumes simultaneously. (write-only register) 6 spkrzc 0 right speaker output zero cross enable 0 = disabled 1 = enabled 5:0 spkr_vol [5:0] 11_1001 right speaker output volume 000000 = -57db 000001 = -56db (? 1db steps) 111001 = 0db (? 1db steps) 111110 = +5db 111111 = +6db table 48 volume control for lon/lop and ron/rop
production data WM8903 w pd, rev 4.5, june 2012 75 analogue outputs the WM8903 has eight analogue output pins: ? headphone outputs, hpoutl and hpoutr ? line outputs, lineoutl and lineoutr ? differential line outputs, lon/lop and ron/rop the output signal paths and associated contro l registers are illustrated in figure 33. headphone outputs ? hpoutl and hpoutr the headphone outputs are designed to drive 16 ? or 32 ? headphones. these outputs are ground- referenced, i.e. no series capacitor is requi red between the pins and the headphone load. they are powered by an on-chip charge pump (see ?charge pump? section). signal volume at the headphone outputs is controlled as shown in table 46. the ground-referenced outputs incorporates a co mmon mode, or ground loop, feedback path which provides rejection of system-related ground noise . the return path for the hpoutl and hpoutr outputs is via hpgnd. this pin must be c onnected to ground for normal operation of the headphone output. no register configuration is required. line outputs ? lineoutl and lineoutr the line outputs are identical to the headphone output s in design. they are ground-referenced and power by the on-chip charge pump. signal volume at the headphone outputs is controlled as shown in table 47. note that these outputs are intended for driving line loads, as the charge pump powering both the headphone and line outputs can only provide sufficient power to drive one set of headphones at any given time. the ground-referenced outputs incorporates a co mmon mode, or ground loop, feedback path which provides rejection of system-related ground noise. the return path for the lineoutl and lineoutr outputs is via linegnd. this pin must be connect ed to ground for normal operation of the line output. no register configuration is required. differential line outputs ? lon/lop and ron/rop the differential line outputs are designed to differ ential line loads, includi ng external loudspeaker drivers. the wm9001 is an ideal component for driv ing loudspeakers from thes e outputs. these pins are referenced to vmid (avdd/2) and are powered directly from the avdd supply. signal volume at the differential line output s is controlled as shown in table 48.
WM8903 production data w pd, rev 4.5, june 2012 76 external components for ground-referenced outputs in the case of the ground referenced outputs hpoutl, hpoutr, lineoutl and lineoutr, it is recommended to connect a zobel network to the audi o output pins for best audio performance in all applications. the components of the zobel netwo rk have the effect of dampening high frequency oscillations or instabilities that can arise out side the audio band under cert ain conditions. possible sources of these instabilities include the inducti ve load of a headphone coil or an active load in the form of an external line amplifier. the capacitance of lengthy cables or pcb tracks can also lead to amplifier instability. the zobel network should comprise a 20 ? resistor and 100nf capacitor in series with each other, as illustrated in figure 34. note that the zobel network is recommended for best audio quality and amplifier stability in all cases. figure 34 zobel network components for hp outl, hpoutr, lineoutl and lineoutr the differential line outputs lop/lo n and rop/ron would, typically, be connected to differential line drivers such as the wm9001 speaker driver. in such applications, a zobel network is not required on these differential line outputs.
production data WM8903 w pd, rev 4.5, june 2012 77 reference voltages and master bias this section describes the analogue reference voltage and bias current controls. it also describes the vmid soft-start circuit for pop-free start-up and shut-down. note that, under the recommended usage conditions of the WM8903, these features will be c onfigured by running the default start-up and shut- down sequences as described in the ?control write sequencer? section. in these cases, the user does not need to set these register fields directly. the analogue circuits in the WM8903 require a mi d-rail analogue reference voltage, vmid. this reference is generated from avdd via a programmable resistor chain. together with the external vmid decoupling capacitor, the programmable resist or chain results in a slow, normal or fast charging characteristic on vmid. this is controlled by vmid_res [1:0], and can be used to optimise the reference for normal operation, low power standby or for fast start-up as described in table 49. for normal operation, the vmid_res field should be set to 01. the analogue circuits in the WM8903 require a bias current. the nor mal bias current is enabled by setting bias_ena. note that the normal bias curr ent source requires vmid to be enabled also. the normal bias current can also be c ontrolled using the isel field as described in table 49. this can be used to reduce power consumption, but may hav e a detrimental impact on audio performance in some usage modes. the default setting is recommended. note that the dac and output pga bias circuits may also be adjusted in order to reduce power consumption. for details, see ?digital-to-analogue converter (d ac)? or ?output signal path?. an alternate bias current source (start-up bias) is provided for pop-free start-up; this is selected using pobctrl (see table 50). note that the defaul t setting of pobctrl selects the start-up bias. the normal bias is only selected when pobctrl is set to logic 0. register address bit label default description r4 (04h) bias control 0 3:2 isel [1:0] 10 master bias control 00 = normal bias x 0.5 01 = normal bias x 0.75 10 = normal bias 11 = normal bias x 1.5 0 bias_ena 0 enables the normal bias current generator (for all analogue functions) 0 = disabled 1 = enabled r5 (05h) vmid control 0 2:1 vmid_res [1:0] 00 vmid divider enable and select 00 = vmid disabled (for off mode) 01 = 2 x 50k ? divider (for normal operation) 10 = 2 x 250k ? divider (for low power standby) 11 = 2 x 5k ? divider (for fast start-up) table 49 reference voltages and master bias enable
WM8903 production data w pd, rev 4.5, june 2012 78 a pop-suppressed start-up requires vmid to be enabled smoothly, without the step change normally associated with the initial stage of the vmid c apacitor charging. a pop-suppressed start-up also requires the analogue bias current to be enabled th roughout the signal path prior to the vmid reference voltage being applied. the WM8903 incor porates pop-suppression ci rcuits which address these requirements. the alternate current source (start-up bias) is enabled by startup_bias_ena. the start-up bias is selected (in place of the normal bias) by pobc trl. it is recommended that the start-up bias is used during start-up, before switching ba ck to the higher quality, normal bias. vmid_io_ena has the same functionality as star tup_bias_ena. the start-up bias is enabled by setting either of these bits. a soft-start circuit is provided in order to control the switch-on of the vmid reference. the soft-start control circuit is enabled by setting vmid_soft. three slew rates are provided, under control of the vmid_soft field. when the soft-start circuit is enabled prior to enabling vmid_res, the reference voltage rises smoothly, without the step change that would otherwise occur. it is recommended that the soft-start circuit and the output signal pat h be enabled before vmid is enabled by vmid_res. a soft shut-down is provided, using the soft-star t control circuit and the start-up bias current generator. the soft shut-down of vmid is achi eved by setting vmid_soft, startup_bias_ena and pobctrl to select the start-up bias current and soft-start circuit prior to setting vmid_res=00. register address bit label default description r4 (04h) bias control 0 4 pobctrl 1 selects the bias current source 0 = normal bias 1 = start-up bias 1 startup_bias_ ena 0 enables the start-up bias current generator 0 = disabled 1 = enabled r5 (05h) vmid control 0 5 vmid_io_ena 0 enables the start-up bias current generator 0 = disabled 1 = enabled (same functionality as startup_bias_ena) 4:3 vmid_soft [1:0] 10 vmid soft start enable / slew rate control 00 = disabled 01 = fast soft start 10 = nominal soft start 11 = slow soft start table 50 soft start control
production data WM8903 w pd, rev 4.5, june 2012 79 pop suppression control the WM8903 incorporates wolfson?s silentsw itch? technology which enables pops normally associated with start-up, shut-down or signal pat h control to be suppressed. to achieve maximum benefit from these features, careful attention is required to the sequence and ti ming of these controls. note that, under the recommended usage conditions of the WM8903, these features will be configured by running the default start-up and s hut-down sequences as described in the ?control write sequencer? section. in these cases, the user does not need to set these register fields directly. the pop suppression controls relating to the h eadphone / line output drivers are described in the ?output signal path? section. disabled input / output control the analogue inputs to the WM8903 and the differentia l line (speaker) outputs are biased to vmid in normal operation. in order to avoid audible pops caused by a disabl ed signal path dropping to agnd, the WM8903 can maintain these connections at vmid when the relevant input or output stage is disabled. this is achieved by connecting a buffered vmid reference to the input or output. the buffered vmid reference is enabled by setting vmid_buf_ena. when the buffered vmid reference is enabled, it is connected to any unused input pins by setting the bufio_ena register bit. when buffered vmid is enabl ed, it is connected to any disabled differential line outputs (speaker driver outputs) by setting vmid_tie_ena. the resistance associated with vmid_tie_ena can be either 500 ? or 20k ? , depending on the vroi register bit. register address bit label default description r5 (05h) vmid control 0 7 vmid_tie_ena 0 vmid buffer to differential lineouts 0 = disabled 1 = enabled (only applies when relevant outputs are disabled, ie. splk=0 or spkr=0. resistance is controlled by vroi.) 6 bufio_ena 0 vmid buffer to unused inputs/outputs 0 = disabled 1 = enabled 0 vmid_buf_ena 0 vmid buffer enable 0 = disabled 1 = enabled r65 (41h) 0 vroi 0 select vmid_tie_ena resistance for disabled differential lineouts 0 = 20k ohm 1 = 500 ohm table 51 disabled input / output control differential line output discharge control the differential line output paths can be actively discharged to agnd through internal resistors if desired. this is desirable at start-up in order to achieve a known output stage condition prior to enabling the soft-start vmid reference voltage. this is also desirable in shut-down to prevent the external connections from being affected by the internal circuits. the differential line outputs (speaker driver outputs) can be dischar ged to agnd by setting spk_discharge. register address bit label default description r65 (41h) 1 spk_discharg e 0 speaker discharge enable 0 = disabled 1 = enable table 52 differential line output discharge control
WM8903 production data w pd, rev 4.5, june 2012 80 charge pump the WM8903 incorporates a dual-mode charge pump which generates the supply rails for the headphone and line output drivers, hpoutl, hpoutr, and lineoutl and lineoutr. the charge pump has a single supply input, cpvdd, and generates split rails vpos and vneg according to the selected mode of operation. the charge pump c onnections are illustrated in figure 35 (see the ?electrical characteristics? sect ion for external component values). an input decoupling capacitor may also be required at cpvdd, depending upon the system configuration. figure 35 charge pump external connections the charge pump is enabled by setting the cp_ena bit. when enabled, the c harge pump adjusts the output voltages (vpos and vneg) as well as the sw itching frequency in order to optimise the power consumption according to the operat ing conditions. this can take two forms, which are selected using the cp_dyn_pwr register bit. ? register control (cp_dyn_pwr = 0) ? dynamic control (cp_dyn_pwr = 1) under register control, the hpoutl_vol, hpoutr_vol, lineoutl_vol and lineoutr_vol register settings are used to contro l the charge pump mode of operation. under dynamic control, the audio signal level in t he dac is used to control the charge pump mode of operation. this is the wolfson ?class w? mode, wh ich allows the power consumption to be optimised in real time, but can only be used if the dac is the only signal source. th is mode should not be used if any of the bypass paths are used to mix analogue inputs into the output signal path. under the recommended usage conditions of the WM8903, the charge pump will be enabled by running the default start-up sequence as descri bed in the ?control write sequencer? section. (similarly, it will be disabled by running the shut-d own sequence.) in these cases, the user does not need to write to the cp_ena bit. the charge pump operating mode defaults to register control; dynamic control may be selected by setting t he cp_dyn_pwr register bit, if appropriate. when digital sidetone is used (see ?digital mixing?), it is recommended that the charge pump operates in register control mode only (cp_dyn_ pwr = 0). this is because the dynamic control mode (class w) does not measure the sidetone signal level and hence the charge pump configuration cannot be optimised fo r all signal conditions when digita l sidetone is enabled; this could lead to signal clipping. the mclk signal must be present for the charge pump to function. the clock division from mclk is handled transparently by the WM8903 without user inte rvention, as long as mclk and sample rates are set correctly (see ?clocking and sample rates? section). the clock divider ratio depends on the sample_rate [3:0], clk_sys_mode [1:0], and clk_sys_rate [3:0] register settings. the charge pump requires a minimum clk_sys frequency of 2.8224mhz.
production data WM8903 w pd, rev 4.5, june 2012 81 the charge pump control fields are described in table 53. register address bit label default description r98 (62h) charge pump 0 0 cp_ena 0 enable charge-pump digits 0 = disable 1 = enable r104 (68h) class w 0 0 cp_dyn_pwr 0 enable dynamic charge pump power control 0 = charge pump controlled by volume register settings 1 = charge pump controlled by real- time audio level table 53 charge pump control dc servo the WM8903 provides a dc servo circuit on the headphone and line outputs in order to remove dc offset from these ground-referenced outputs. when enabled, the dc servo ensures that the dc level of these outputs remains within 1.5mv of ground. removal of the dc offset is important because any deviation from gnd at the output pin will cause current to flow through the load under quiescent conditions, resulting in increased power consumption. additionally, the presence of dc offsets can result in audible pops and clicks at power up and power down. the recommended usage of the dc servo is initialis ed by running the default start-up sequence as described in the ?control write sequencer? sect ion. the default start-up sequence selects start_stop servo mode, which causes a one-o ff correction to be performed, after which the measured dc offset is then maintained on the headphone and line outputs. if a different usage is required, e.g. if one or more of the outputs is not in use, or if periodic dc offset correction is required, then the default start-up sequence may be modified according to specific requirements. the relevant contro l fields are defined in table 54 . if dc offset correction is not required on any output, then dcs_master_ena should be set to 0. setting this field to 0 before running the start-up sequence will disable the dc servo on all outputs. if dc offset correction is only required on selected channels, then dcs_ena should be set accordingly. setting this field to 1111b enables t he dc servo on all outputs. setting any bit to 0 disables the dc servo on t he corresponding output. disabli ng the dc servo on unused outputs reduces power consumption in the device. to modify this within the start-up sequence, the data in wseq address 23 and wseq address 24 s hould be updated (see ?control write sequencer?) before running the sequence. if periodic updates to the dc offset correction is required, then dcs_m ode should be modified. setting this field to 11b selects start_update servo mode, which causes the dc offset to be measured and corrected on a periodic basis. the def ault time between updates is approximately 10 minutes. scheduling periodic updat es enables the WM8903 to compensate for any change in dc offsets which might have occurred due to power supply dri ft or other factors. to modify this within the start-up sequence, the data in wseq a ddress 22 should be updated (see ?control write sequencer?) before running the sequence.
WM8903 production data w pd, rev 4.5, june 2012 82 register address bit label default description r67 (43h) dc servo 0 4 dcs_master_ena 1 dc servo master control 0 = dc servo reset 1 = dc servo enabled 3:0 dcs_ena [3:0] 0000 dc servo enable [3] - hpoutl enable [2] - hpoutr enable [1] - loutl enable [0] - loutr enable r69 (45h) dc servo 2 1:0 dcs_mode [1:0] 00 dc servo mode 00 = write_stop 01 = write_update 10 = start_stop 11 = start_update table 54 dc servo control to reduce power consumption when unused audio outputs are disabl ed, the dc servo correction should also be disabled. the wm 8903 provides the capability to quickly resume the necessary dc servo correction when the outputs are re-enabled, without the time delay associated with the start_stop mode of dc servo operation. if the dc servo correction is di sabled using the dcs_ena bits, but the dcs_master_ena bit is maintained at 1, then the dc servo will retain the late st correction values in its memory. these values will be re-applied when the dc servo is later enabled via the dcs_ena bits. an alternative method to apply known correction setti ngs is to read the correction values from the WM8903 register map and to store these for later us e. after dc offset correction has been performed, the applicable correction values can be read from t he fields in the servo readback registers r81 to r84 described in table 55. setting dcs_mode to 00b or 01b selects write_stop mode and write_update mode respectively. write_stop mode is similar to start_stop mode, except that the dc servo correction factors are read from internal registers, instead of being calculated from the measured output conditions. in the same way, write_upda te mode is similar to start_update mode. when the dc servo is commanded to one of these modes , the initial dc offset correction values are read from the _write_val field in regi sters r71 to r74 described in table 55. selecting write_stop or write_update mode app lies initial settings which should be written to registers r71 to r74 before the dc servo is enabled. in write_stop mode, no further dc correction is applied. in write_update mode, the dc servo will periodically measure and adjust the dc offset correction. similar to start_up date mode, the default time between updates is approximately 10 minutes.
production data WM8903 w pd, rev 4.5, june 2012 83 register address bit label default description r71 (47h) dc servo 4 7:0 dcs_hpoutl_write_val [7:0] 0000_0000 value to send to left headphone output servo in a write mode two?s complement format. lsb is 0.25mv. range is +/-32mv r72 (48h) dc servo 5 7:0 dcs_hpoutr_write_val [7:0] 0000_0000 value to send to right headphone output servo in a write mode two?s complement format. lsb is 0.25mv. range is +/-32mv r73 (49h) dc servo 6 7:0 dcs_loutl_write_val [7:0] 0000_0000 value to send to left line output servo in a write mode two?s complement format. lsb is 0.25mv. range is +/-32mv r74 (4ah) dc servo 7 7:0 dcs_loutr_write_val [7:0] 0000_0000 value to send to right line output servo in a write mode two?s complement format. lsb is 0.25mv. range is +/-32mv r81 (51h) dc servo readback 1 7:0 dcs_hpoutl_integ [7:0] 0000_0000 readback value on left headphone output servo. two?s complement format. lsb is 0.25mv. range is +/-32mv (read-only register) r82 (52h) dc servo readback 2 7:0 dcs_hpoutr_integ [7:0] 0000_0000 readback value on headphone right output servo. two?s complement format. lsb is 0.25mv. range is +/-32mv (read-only register) r83 (53h) dc servo readback 3 7:0 dcs_loutl_integ [7:0] 0000_0000 readback value on left line output servo. two?s complement format. lsb is 0.25mv. range is +/-32mv (read-only register) r84 (54h) dc servo readback 4 7:0 dcs_loutr_integ [7:0] 0000_0000 readback value on right line output servo. two?s complement format. lsb is 0.25mv. range is +/-32mv (read-only register) table 55 dc servo initial settings and readback
WM8903 production data w pd, rev 4.5, june 2012 84 digital audio interface the digital audio interface is used for inputti ng dac data into the WM8903 and outputting adc data from it. the digital audio in terface uses four pins: ? adcdat: adc data output ? dacdat: dac data input ? lrc: dac and adc data alignment clock ? bclk: bit clock, for synchronisation the clock signals bclk and lrclk can be outputs when the WM8903 operates as a master, or inputs when it is a slave (see ?maste r and slave mode operation? below). note that the bclk pin can also support other functions, as descri bed under ?general purpose input/output (gpio)?. bclk is the default f unction on this pin (gp5_fn = 1h). under default conditions, the other gpio control fi elds for this pin have no effect. four different audio data formats are supported: ? left justified ? right justified ? i2s ? dsp mode all four of these modes are msb first. they ar e described in ?audio data formats (normal mode)? below. refer to the ?signal timing require ments? section for timing information. time division multiplexing (tdm) is available in all four data format modes. the WM8903 can be programmed to send and receive data in one of two time slots. pcm operation is supported using the dsp mode. master and slave mode operation the WM8903 digital audio interface can operate in ma ster or slave mode, as shown in figure 36 and figure 37. figure 36 master mode figure 37 slave mode in master mode, bclk is derived from clk_sy s via a programmable division set by bclk_div. in master mode, lrc is derived from bclk via a programmable division set by lrclk_rate. the bclk input to this divider may be internal or external, allowing mixed master and slave modes.
production data WM8903 w pd, rev 4.5, june 2012 85 the direction of these signals and the clock frequencie s are controlled as described in the ?digital audio interface control? section. bclk and lrc can be enabled as outputs in slave m ode, allowing mixed master/slave operation - see ?digital audio interface control?. operation with tdm time division multiplexing (tdm) allows multiple devices to transfer data simultaneously on the same bus. the WM8903 adcs and dacs support tdm in ma ster and slave modes for all data formats and word lengths. tdm is enabled and confi gured using register bits defined in the ?digital audio interface control? section. WM8903 processor WM8903 or similar codec adcdat lrc dacdat bclk adcdat lrc dacdat bclk WM8903 processor WM8903 or similar codec adcdat lrc dacdat bclk adcdat lrc dacdat bclk figure 38 tdm with WM8903 as master figure 39 tdm with other codec as master WM8903 processor WM8903 or similar codec adcdat lrc dacdat bclk adcdat lrc dacdat bclk figure 40 tdm with processor as master note: the WM8903 is a 24-bit device. if the user operates the WM8903 in 32-bit mode then the 8 lsbs will be ignored on the receiving side and not driven on the transmitting side. it is therefore recommended to add a pull-down resistor if necessary to the dacdat line and the adcdat line in tdm mode.
WM8903 production data w pd, rev 4.5, june 2012 86 bclk frequency the bclk frequency is controlled relative to clk_sy s by the bclk_div divider. internal clock divide and phase control mechanisms ensure that the bc lk and lrc edges will occur in a predictable and repeatable position relative to each other and rela tive to the data for a given combination of dac/adc sample rate and bclk_div settings. bclk_div is defined in the ?digital audio interf ace control? section. see also the ?clocking and sample rates? section for more information. audio data formats (normal mode) in right justified mode, the lsb is available on t he last rising edge of bclk before a lrc transition. all other bits are transmitted before (msb fi rst). depending on word length, bclk frequency and sample rate, there may be unused bclk cycles after each lrc transition. figure 41 right justified audio interface (assuming n-bit word length) in left justified mode, the msb is available on the first rising edge of bclk following a lrc transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unus ed bclk cycles before each lrc transition. figure 42 left justified audio interface (assuming n-bit word length) in i 2 s mode, the msb is available on the second risi ng edge of bclk following a lrc transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of one sample and the msb of the next.
production data WM8903 w pd, rev 4.5, june 2012 87 figure 43 i2s justified audio interface (assuming n-bit word length) in dsp mode, the left channel msb is available on either the 1 st (mode b) or 2 nd (mode a) rising edge of bclk (selectable by aif_lrclk_inv) fo llowing a rising edge of lrc. right channel data immediately follows left channel data. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of the right channel data and the next sample. in device master mode, the lrc output will resemble the frame pulse shown in figure 44 and figure 45. in device slave mode, figure 46 and figure 47, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one bclk period before the rising edge of the next frame pulse. figure 44 dsp mode audio interface (mode a, aif_lrclk_inv=0, master) figure 45 dsp mode audio interface (mode b, aif_lrclk_inv=1, master)
WM8903 production data w pd, rev 4.5, june 2012 88 figure 46 dsp mode audio interface (mode a, aif_lrclk_inv=0, slave) figure 47 dsp mode audio interface (mode b, aif_lrclk_inv=1, slave) pcm operation is supported in dsp interface mode. WM8903 adc data that is output on the left channel will be read as mono pcm data by the receiving equipment. mono pcm data received by the WM8903 will be treated as left channel data. this dat a may be routed to the left/right dacs as described in the ?digital mixing? section. audio data formats (tdm mode) tdm is supported in master and slave mode and is enabled by register bits aifadc_tdm and aifdac_tdm. all audio interface data formats suppor t time division multiplexing (tdm) for adc and dac data. two time slots are available (slot 0 and slot 1) , selected by register bits aifadc_tdm_chan and aifdac_tdm_chan which control time slots for the adc data and the dac data. when tdm is enabled, the adcdat pin will be tri-st ated immediately before and immediately after data transmission, to allow another audio device to dr ive this signal line for the remainder of the sample period. it is important that two audio devices do not attempt to drive the data pin simultaneously, as this could result in a short circ uit. see ?audio interface ti ming? for details of the adcdat output relative to bclk signal. note that it is possible to ensure a gap exists between transmissions by setting the transmi tted word length to a value higher than the actual length of the data. for example, if 32-bit word length is sele cted where only 24-bit data is available, then the WM8903 interface will tri-state after transmission of t he 24-bit data; this creates an 8-bit gap after the WM8903?s tdm transmission slot. when tdm is enabled, bclk frequency must be high enough to allow data from both time slots to be transferred. the relative timing of slot 0 and sl ot 1 depends upon the selected data format as shown in figure 48 to figure 52.
production data WM8903 w pd, rev 4.5, june 2012 89 figure 48 tdm in right-justified mode figure 49 tdm in left-justified mode figure 50 tdm in i 2 s mode figure 51 tdm in dsp mode a
WM8903 production data w pd, rev 4.5, june 2012 90 figure 52 tdm in dsp mode b digital audio interface control the register bits controlling audio data format, wo rd length left/right channel data source and tdm are summarised in table 56. register address bit label default description r24 (18h) audio interface 0 12 dacl_datinv 0 left dac invert 0 = left dac output not inverted 1 = left dac output inverted 11 dacr_datinv 0 right dac invert 0 = right dac output not inverted 1 = right dac output inverted 7 aifadcl_src 0 left digital audio channel source 0 = left adc data is output on left channel 1 = right adc data is output on left channel 6 aifadcr_src 1 right digital audio channel source 0 = left adc data is output on right channel 1 = right adc data is output on right channel 5 aifdacl_src 0 left dac data source select 0 = left dac outputs left channel data 1 = left dac outputs right channel data 4 aifdacr_src 1 right dac data source select 0 = right dac outputs left channel data 1 = right dac outputs right channel data r25 (19h) audio interface 1 13 aifdac_tdm 0 dac tdm enable 0 = normal dacdat operation 1 = tdm enabled on dacdat 12 aifdac_tdm_c han 0 dacdat tdm channel select 0 = dacdat data input on slot 0 1 = dacdat data input on slot 1 11 aifadc_tdm 0 adc tdm enable 0 = normal adcdat operation 1 = tdm enabled on adcdat
production data WM8903 w pd, rev 4.5, june 2012 91 register address bit label default description 10 aifadc_tdm_c han 0 adcdat tdm channel select 0 = adcdat outputs data on slot 0 1 = adcdat output data on slot 1 7 aif_bclk_inv 0 bclk invert 0 = bclk not inverted 1 = bclk inverted 4 aif_lrclk_inv 0 lrc polarity / dsp mode a-b select. right, left and i 2 s modes ? lrc polarity 0 = not inverted 1 = inverted dsp mode ? mode a-b select 0 = msb is available on 2nd bclk rising edge after lrc rising edge (mode a) 1 = msb is available on 1st bclk rising edge after lrc rising edge (mode b) 3:2 aif_wl [1:0] 00 digital audio interface word length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits 1:0 aif_fmt [1:0] 10 digital audio interface format 00 = right justified 01 = left justified 10 = i2s 11 = dsp r38 (26h) adc digital 0 1 adcl_datinv 0 left adc invert 0 = left adc output not inverted 1 = left adc output inverted 0 adcr_datinv 0 right adc invert 0 = right adc output not inverted 1 = right adc output inverted table 56 digital audio interface data control note that the WM8903 is a 24-bit device. in 32-bi t mode (aif_wl=11), the 8 lsbs are ignored on the receiving side and not driv en on the transmitting side. bclk and lrclk control the audio interface can be programmed to operat e in master mode or slave mode using the bclk_dir and lrclk_dir register bits. in master mode, the bclk and lrclk signals are generated by the WM8903 when any of the adcs or dacs is enabled. in slave mode, the bclk and lrclk clock outputs are disabled by default to allo w another digital audio interface to drive these pins. it is also possible to force the bclk or lrclk signals to be output using bclk_dir and lrclk_dir, allowing mixed master and slave m odes. the bclk_dir and lrclk_dir fields are defined in table 57.
WM8903 production data w pd, rev 4.5, june 2012 92 when bclk is not selected (gp5_fn 1), the WM8903 uses the mclk input as the bit clock, provided that bclk_dir is set to 0 to configur e bclk as an input, ie. bclk slave mode. this configuration can offer power c onsumption benefits in addition to flexibility of gpio functionality, when the bclk pin is an output (bclk_dir=1), bclk is derived from the internal clk_sys signal (see ?clocking and sample rates?). in this case, the bclk frequency is controlled in relation to clk_sys by the bclk_div register field. w hen bclk is an input, bclk_div has no effect. when the lrc pin is an output (lrclk_dir=1), lrc is derived from bclk (irrespective of whether bclk is an input or output). in this case, the l rc frequency is controlled in relation to bclk by the lrclk_rate register field. when lrc is an input, lrclk_rate has no effect. bclk_div and lrclk_rate are defined in table 57. the clocking scheme is illustrated in the ?clocking and sample rates? section - see figure 55. register address bit label default description r25 (19h) audio interface 1 9 lrclk_dir 0 audio interface lrc direction 0 = lrc is input 1 = lrc is output 6 bclk_dir 0 audio interface bclk direction 0 = bclk is input 1 = bclk is output r26 (1ah) audio interface 2 4:0 bclk_div [4:0] 0_1000 bclk frequency (master mode) 00000 = clk_sys 00001 = reserved 00010 = clk_sys / 2 00011 = clk_sys / 3 00100 = clk_sys / 4 00101 = clk_sys / 5 00110 = reserved 00111 = clk_sys / 6 01000 = clk_sys / 8 (default) 01001 = clk_sys / 10 01010 = reserved 01011 = clk_sys / 12 01100 = clk_sys / 16 01101 = clk_sys / 20 01110 = clk_sys / 22 01111 = clk_sys / 24 10000 = reserved 10001 = clk_sys / 30 10010 = clk_sys / 32 10011 = clk_sys / 44 10100 = clk_sys / 48 r27 (1bh) audio interface 3 10:0 lrclk_rate [10:0] 000_0010 _0010 lrc rate (master mode) lrc clock output = bclk / lrclk_rate integer (lsb = 1) valid range: 8 to 2047 50:50 lrclk duty cycle is only guaranteed with even values (8, 10, ? 2046). table 57 digital audio interface clock control
production data WM8903 w pd, rev 4.5, june 2012 93 companding the WM8903 supports a-law and ? -law companding on both transmit (adc) and receive (dac) sides as shown in table 58. register address bit label default description r24 (18h) audio interface 0 3 adc_comp 0 adc companding enable 0 = disabled 1 = enabled 2 adc_compmo de 0 adc companding type 0 = -law 1 = a-law 1 dac_comp 0 dac companding enable 0 = disabled 1 = enabled 0 dac_compmo de 0 dac companding type 0 = -law 1 = a-law table 58 companding control companding uses a piecewise linear approximation of the following equations (as set out by itu-t g.711 standard) for data compression: ? -law (where ? =255 for the u.s. and japan): f(x) = ln( 1 + ? |x|) / ln( 1 + ? ) -1 x 1 a-law (where a=87.6 for europe): f(x) = a|x| / ( 1 + lna) x 1/a f(x) = ( 1 + lna|x|) / (1 + lna) 1/a x 1 the companded data is also inverted as recommended by the g.711 standard (all 8 bits are inverted for ? -law, all even data bits are inverted for a-law). t he data will be transmitted as the first 8 msbs of data. companding converts 13 bits ( ? -law) or 12 bits (a-law) to 8 bits using non-linear quantization. this provides greater precision for low amplitude signals than for high amplitude signals, resulting in a greater usable dynamic range than 8 bit linear quant ization. the companded signal is an 8-bit word comprising sign (1 bit), exponent (3 bits) and mantissa (4 bits). 8-bit mode is selected whenever dac_comp=1 or adc_comp=1. the use of 8-bit data allows samples to be passed using as few as 8 bclk cycl es per lrc frame. when using dsp mode b, 8-bit data words may be transferred consec utively every 8 bclk cycles. 8-bit mode (without companding) may be enabled by setting dac_compmode=1 or adc_compmode=1, when dac_comp=0 and adc_comp=0. bit7 bit [6:4] bit [3:0] sign exponent mantissa table 59 8-bit companded word composition
WM8903 production data w pd, rev 4.5, june 2012 94 u-law companding 0 20 40 60 80 100 120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised input companded output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised output figure 53 -law companding a-law companding 0 20 40 60 80 100 120 0 0.2 0.4 0.6 0.8 1 normalised input companded output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised output figure 54 a-law companding loopback setting the loopback register bit enables digital l oopback. when this bit is set, the adc digital data output is routed to the dac digital data input path. the digital audio interface input (dacdat) is not used when loopback is enabled. register address bit label default description r24 (18h) audio interface 0 8 loopback 0 digital loopback function 0 = no loopback 1 = loopback enabled (adc data output is directly input to dac data input) table 60 loopback control
production data WM8903 w pd, rev 4.5, june 2012 95 note: when the digital sidetone is enabled, adc dat a will continue to be added to dac data when loopback is enabled. clocking and sample rates the WM8903 supports a wide range of standard audio sa mple rates from 8khz to 96khz. when the dac and adc are both enabled, they operate at the same sample rate, f s . oversample rates of 64fs or 128fs are supported (based on a 48khz sample rate). note that simultaneous adc and dac operation at 88.2khz or 96khz is not possible. digital microphone operation is not supported at 88.2khz or 96khz sample rates. the clocking options for 88.2khz or 96khz adc operation are restricted to specific configurat ions only, as detailed in this section. the internal clocks for the WM8903 are all derived fr om a common internal clock source, clk_sys. this clock is the reference for the adcs, dacs, d sp core functions, digital audio interface, dc servo control and other internal functions. clk_sys can either be derived directly from mclk, or may be generated from a frequency locked loop (fll) using mclk, bclk or lrc as a refer ence. many commonly-used audio sample rates can be derived directly from typical mclk frequencies; the fll provides additional flexibility for a wide range of mclk frequencies. to avoid audible glitches , all clock configurations must be set up before enabling playback. the fll can be used to generat e a free-running clock in the absence of an external reference source; see ?frequenc y locked loop (fll)? for further details. the WM8903 supports automatic clocking configurati on. the programmable dividers associated with the adcs, dacs, dsp core functions and dc serv o are configured automatically, with values determined from the sample_rate, clk_sys_rate and clk_sys_mode fields. note that the user must also configure t he digital audio interface. a 256khz clock, supporting the control write s equencer, micbias current detect filtering and a number of internal functions, is derived from cl k_sys. this clock is enabled by wsmd_clk_ena. a slow clock, toclk, is used to de-bounce the butt on/accessory detect inputs, and to set the timeout period for volume updates when zero-cross detect is used. this clock is enabled by to_ena. the charge pump and dc servo control f unctions are clocked from clk_sys. in master mode, bclk is derived from clk_sys via a programmable divider set by bclk_div. in master mode, the lrc is derived from bclk vi a a programmable divider lrclk_rate. the lrc can be derived from an internal or external bclk source, allowing mixed master/slave operation. the overall clocking scheme for the WM8903 is illustra ted in figure 55. note that bclk and lrc are described in the ?digital audio interface? section.
WM8903 production data w pd, rev 4.5, june 2012 96 fll fll_clk_src selects the input reference for fll oscillator. the fll clock output may be selected on any gpio pin. clk_sys internal clocks are derived from clk_sys, which can be derived from mclk or from the fll output. the clk_sys source is selected by clk_src_sel. a selectable divide by 2 option is provided using mclkdiv2. the internal clocks are enabled by clk_sys_ena. clk_dsp dsp clocks are derived from clk_sys. these are enabled by clk_dsp_ena. dac clocks dac dsp clock is derived from dsp_clk automatically. alternate settings are available using dacosr. adc clocks adc dsp clock is derived from dsp_clk automatically. alternate settings are available using adc_osr128. other clocks the clocking for the dc servo, charge pump and other internal functions is derived from clk_sys automatically. 256khz clock the 256khz clock for the control write sequencer and micbias current detect function is derived from clk_sys automatically. this is enabled by wsmd_clk_ena. toclk control the slow clock for volume update timeout and gpio / accessory detect de-bounce is enabled by to_ena. lrc rate lrc rate is set by lrclk_rate in master mode. the bclk input to this divider may be internal or external. bclk rate bclk rate is set by bclk_div in master mode. clk_dsp_ena clk_dsp 64fs or 128fs f/n adc f/n dac f/n automatic dsp clocking control sample_rate [2:0] clk_sys_rate [3:0] the dac, adc, 256khz, and dc servo clocks are configured automatically according to sample_rate, clk_sys_rate and clk_sys_mode. clk_sys f/n clocking for dc servo, charge pump and other circuits 256khz clock to control write sequencer and micbias current detect filtering to_ena button/accessory detect de-bounce, volume update timeout r1ah[4:0] bclk_div[4:0] (master mode) 00000 = sysclk 00001 = sysclk / 1.5 00010 = sysclk / 2 00011 = sysclk / 3 00100 = sysclk / 4 00101 = sysclk / 5 00110 = sysclk / 5.5 00111 = sysclk / 6 01000 = sysclk / 8 01001 = sysclk / 10 01010 = sysclk / 11 01011 = sysclk / 12 01100 = sysclk / 16 01101 = sysclk / 20 01110 = sysclk / 22 bclk_div [3:0] lrclk_rate [10:0] lrc bclk f/n clk_sys_mode [1:0] f/n bclk_dir lrclk_dir f/n master mode clock outputs f/n dac_osr adc_osr128 wsmd_clk_ena f/n mclk f/n clk_sys_ena mclkdiv2 fll f ref f out clk_src_sel bclk lrc fll_clk_src gpio figure 55 clocking overview
production data WM8903 w pd, rev 4.5, june 2012 97 clk_sys control the clk_src_sel bit is used to select the sour ce for clk_sys. the source may be either the mclk input or the fll output. the selected source may be adjusted by the mclkdiv2 divider to generate clk_sys. these register fields are described in table 61. see ?frequency locked loop (fll)? for more details of the frequency locked loop clock generator. the clk_sys signal is enabled by register bit clk_ sys_ena. this bit should be set to 1 for normal operation with mclk applied. this bit should be set to 0 when reconfiguring clock sources. it is not recommended to change clk_src_sel while the clk_sys_ena bit is set. the following operating frequency limits must be obser ved when configuring clk_sys. failure to observe these limits will result in degraded noise performance and/or incorrect adc/dac functionality. ? if dac_osr = 0 then clk_sys ? 3mhz ? if dac_osr = 1 then clk_sys ? 6mhz for dac operation up to 48khz sample rate, the following clk_sys limits are applicable. these conditions are applicable whenever da cl_ena = 1 or dacr_ena = 1. note that the adc operation limits must also be obs erved if either adc is enabled. see ?digital-to- analogue converter (dac)? for definit ions of dac_mono and dac_osr. ? if dac_mono = 0 and dac_osr = 0, then clk_sys ? 128 x fs ? if dac_mono = 0 and dac_osr = 1, then clk_sys ? 256 x fs ? if dac_mono = 1 and dac_osr = 0, then clk_sys ? 64 x fs ? if dac_mono = 1 and dac_osr = 1, then clk_sys ? 128 x fs for adc operation up to 48khz sample rate, the following clk_sys limits are applicable. these conditions are applicable whenever a dcl_ena = 1 or adcr_ena = 1. note that the dac operation limits must also be observed if either dac is enabled. see ?analogue-to- digital converter (adc)? for the definition of adc_osr. ? if adc_osr = 0, then clk_sys ? 128 x fs ? if adc_osr = 1, then clk_sys ? 256 x fs further requirements for 88.2khz and 96khz operation are provided later in this section. note that simultaneous adc and dac operation at 88. 2khz or 96khz is not possible. the clocking of the adc and dac circuits is derived from clk_dsp, which is enabled by clk_dsp_ena. (note that clk_sys must also be enabled.) a 256khz clock required for the control write s equencer and micbias current detect filtering is derived from clk_sys. the 256khz clock is enabled by wsmd_clk_ena. the slow clock (toclk) required for input signal de-bouncing and volume update timeout functions is derived from the 256khz clock. the toclk clock is enabled by to_ena.
WM8903 production data w pd, rev 4.5, june 2012 98 the clk_sys control register fields are defined in table 61. register address bit label default description r20 (14h) clock rates 0 0 mclkdiv2 0 enables divide by 2 on mclk 0 = clk_sys = mclk 1 = clk_sys = mclk / 2 r21 (15h) clock rates 1 15 clk_src_sel 0 sysclk source select 0 = mclk 1 = fll output r22 (16h) clock rates 2 2 clk_sys_ena 0 system clock enable 0 = disabled 1 = enabled 1 clk_dsp_ena 0 dsp clock enable 0 = disabled 1 = enabled 0 to_ena 0 zero cross timeout enable 0 = disabled 1 = enabled r108 (6ch) write sequencer 0 8 wsmd_clk_e na 0 write sequencer / mic detect clock enable. 0 = disabled 1 = enabled table 61 mclk and clk_sys control control interface clocking register map access is possible with or without a master clock (mclk). however, if clk_sys_ena has been set to 1, then a master clock must be pres ent for control register read/write operations. if clk_sys_ena = 1 and mclk is not present, then r egister access will be unsuccessful. (note that read/write access to register r22, contai ning clk_sys_ena, is always possible.) if it cannot be assured that mclk is present when a ccessing the register map, then it is required to set clk_sys_ena = 0 to ensure correct operation. it is possible to use the WM8903 analogue bypass paths to the differential line outputs (lon/lop and ron/rop) without mclk. note that mclk is always required when using hpoutl, hpoutr, lineoutl or lineoutr. automatic clocking configuration the WM8903 supports a wide range of standard audio sample rates from 8khz to 96khz. the automatic clocking configuration mode simplifies t he configuration of the clock dividers in the WM8903 by deriving most of the necessary parameter s from a minimum number of user registers. the sample_rate field selects the sample rate, fs, of the adc and dac. note that the same sample rate always applies to the adc and dac. the clk_sys_rate and clk_sys_mode fields must be set according to the ratio of clk_sys to fs. (note that the internal clock clk_sys is der ived from mclk as controlled by mclkdiv2). when these fields are set correctly, the sample rate de coder circuit automatically determines the clocking configuration for all other circuits within the WM8903.
production data WM8903 w pd, rev 4.5, june 2012 99 the dsp clocking is enabled by clk_dsp_ena; s ee table 61 for details of this register. register address bit label default description r21 (15h) clock rates 1 13:10 clk_sys_rat e [3:0] 0011 clk_sys_rate and clk_sys_mode together determine the clock division ratio (clk_sys / fs); see table 63 9:8 clk_sys_mod e [1:0] 00 3:0 sample_rate [3:0] 1000 selects the sample rate (fs) 0000 = 8khz 0001 = 11.025khz 0010 = 12khz 0011 = 16khz 0100 = 22.05khz 0101 = 24khz 0110 = 32khz 0111 = 44.1khz 1000 = 48khz 1001 = 88.2khz (not available for digital microphone. not used for 88.2khz adc.) 1010 = 96khz (not available for digital microphone. not used for 96khz adc) 1011 to 1111 = reserved if the desired sample rate is not listed in this table, then the closest alternative should be chosen. table 62 automatic clocking configuration control 00 01 10 (default) 0000 64 68 125 0001 128 136 125 0010 192 204 250 0011 256 272 250 0100 384 408 375 0101 512 544 500 0110 768 816 750 0111 1024 1088 1000 1000 1408 1496 1000 1001 1536 1632 1500 1010 to 1111 clk_sys_mode clk_sys_rate available clk_sys / f s ratios reserved (usb modes) table 63 sample rate decoder control the clock division ratios available with clk_ sys_mode = 00 are suitable for use with standard audio master clocks. for example, with a 12.288mhz clk_sys and 48khz sample rate, the clk_sys to fs ratio is 256. in this case, the required setting for clk_sys_rate is 0011, as shown above.
WM8903 production data w pd, rev 4.5, june 2012 100 usb clocking mode the clock division ratios with clk_sys_mode = 01 or clk_sys_mode = 10 allow compatibility with a 12mhz usb clock, at sample rates up to 48khz. for example, with a 12mhz (usb) clock and 8khz sample rate, the clk_sys to fs ratio is 1500. in this case, the required setting for clk_sys_rate is 1001. note that 44.1khz and related sample rates ar e approximate when derived from a usb clock. for example, with a 12mhz mclk and a division rati o of 272, the exact sample rate obtained is 44.118khz rather than 44.1khz. this 0.04% offset is inaudible and can be i gnored. 48khz and related sample rates are exact in all modes of operat ion, provided that mclk itself is exact. adc / dac operation at 88.2k / 96k the WM8903 supports adc or dac operation at 88.2k hz and 96khz sample rates. this section details specific conditions app licable to these operating modes. note that simultaneous adc and dac operation at 88.2khz or 96khz is not possible. for dac operation at 88.2khz or 96khz sample ra tes, the available clocking configurations are detailed in table 64. note that, for dac operation at 88.2khz or 96khz sample rates, the adcs must both be disabled (adcl_ena = 0 and adcr_ena = 0). also, the dac_osr register should be set to 0. the clk_sys frequency is derived from mclk. note that the maximum mclk frequency is defined in the ?signal timing requirements? section. sample rate register configuration clk_sys / fs ratio 88.2khz sample_rate = 1001 clk_sys_rate = 0001 clk_sys_mode = 00 128 x fs clk_sys_mode = 01 136 x fs clk_sys_mode = 10 125 x fs 96khz sample_rate = 1010 clk_sys_rate = 0001 clk_sys_mode = 00 128 x fs clk_sys_mode = 10 125 x fs table 64 dac operation at 88.2khz and 96khz sample rates for adc operation at 88.2khz or 96khz sample ra tes, the available clo cking configurations are detailed in table 65. note that adc operation at these sample rates is achieved by setting the sam ple_rate field to half the required sample rate (eg. select 48khz for 96k hz mode). in these modes, the bclk_div field is set to select bclk at double the normal rate. note that, for adc operation at 88.2khz or 96khz sample rates, the dacs must both be disabled (dacl_ena = 0 and dacr_ena = 0). the clk_sys frequency is derived from mclk. note that the maximum mclk frequency is defined in the ?signal timing requirements? section. sample rate register configuration clk_sys / fs ratio 88.2khz sample_rate = 0111 clk_sys_rate = 0001 clk_sys_mode = 00 bclk_div = 00010 lrclk_rate = 040h 128 x fs 96khz sample_rate = 1000 clk_sys_rate = 0001 clk_sys_mode = 00 bclk_div = 00010 lrclk_rate = 040h 128 x fs table 65 adc operation at 88.2khz and 96khz sample rates
production data WM8903 w pd, rev 4.5, june 2012 101 digital microphone (dmic) operation when gpio1/dmic_lr is configured as dmic_lr clock output, the WM8903 outputs a clock which supports digital microphone operation at a multiple of the adc sampling rate. the precise clock frequency varies according to the mclk frequency, the sample_rate field and other settings. the clock frequency is always within the range 1mhz - 3mhz, and some examples are shown in table 66. sample rate clk_sys clk_sys ratio dmic_lr frequency dmic_lr ratio 8khz 12.288mhz 1536fs 1.024mhz 128fs 8khz 12mhz 1500fs 1.200mhz 150fs 16khz 12.288mhz 768fs 2.048mhz 128fs 16khz 12mhz 750fs 2.400mhz 150fs 48khz 12.288mhz 256fs 1.536mhz 32fs 48khz 12mhz 250fs 2.400mhz 50fs 44.1khz 11.2896mhz 256fs 2.822mhz 64fs 44.1khz 12mhz 272fs 3.000mhz 68fs 32khz 12mhz 375fs 2.400mhz 75fs 24khz 12mhz 500fs 2.400mhz 100fs 12khz 12mhz 1000fs 1.500mhz 125fs table 66 digital microphone clock note that the 88.2khz and 96khz sample rate se ttings are not valid for digital microphone operation. frequency locked loop (fll) the integrated fll can be used to generate clk_sys from a wide variety of different reference sources and frequencies. the fll can use either mclk , bclk or lrc as its reference, which may be a high frequency (eg. 12.288mhz) or low frequency (eg. 32.768khz) reference. the fll is tolerant of jitter and may be used to generate a stable clk_sys from a less stable input signal. the fll characteristics are summarised in ?electrical characteristics?. note that the fll can be used to generate a fr ee-running clock in the absence of an external reference source. this is described in t he ?free-running fll clock? section below. the fll is enabled using the fll_ena register bi t. note that, when changing fll settings, it is recommended that the digital circ uit be disabled via fll_ena and then re-enabled after the other register settings have been updated. when changing the input reference frequency f ref , it is recommended the fll be reset by setting fll_ena to 0. the fll_clk_src field allows mclk, bclk or lrc to be selected as the input reference clock. the field fll_clk_ref_div provides the option to divide the input reference (mclk, bclk or lrc) by 1, 2, 4 or 8. this field should be set to br ing the reference down to 13.5mhz or below. for best performance, it is recommended that the highest possible frequency - within the 13.5mhz limit - should be selected. the field fll_ctrl_rate controls in ternal functions within the fll; it is recommended that only the default setting be used for this parameter. fll_gain c ontrols the internal loop gain and should be set to the recommended value quoted in table 69. the fll output frequency is directly determined from fll_fratio, fll_outdiv and the real number represented by fll_n and fll_k. the field fll_n is an integer (lsb = 1); fll_k is the fractional portion of the number (msb = 0.5). the fr actional portion is only va lid in fractional mode when enabled by the field fll_frac. it is recommended that fractional mode (fll_frac = 1) is selected at all times. power consumption in the fll is reduced in integer mode; howev er, the performance may also be reduced, with increased noise or jitter on the output. if low power consumption is required, then fll se ttings must be chosen when n.k is an integer (ie. fll_k = 0). in this case, the fractional mode can be disabled by setting fll_frac = 0.
WM8903 production data w pd, rev 4.5, june 2012 102 for best fll performance, a non-integer value of n.k is required. in this case, the fractional mode must be enabled by setting fll_frac = 1. the fll settings must be adjusted, if necessary, to produce a non-integer value of n.k. the fll output frequency is generated according to the following equation: f out = (f vco / fll_outdiv) the fll operating frequency, f vco is set according to the following equation: f vco = (f ref x n.k x fll_fratio) see table 69 for the coding of t he fll_outdiv and fll_fratio fields. f ref is the input frequency, as determined by fll_clk_ref_div. f vco must be in the range 90-100 mhz. frequencies outside this range cannot be supported. note that the output frequencies that do not lie within the ranges quoted above cannot be guaranteed across the full range of device operating temperatures. in order to follow the above requirements for f vco , the value of fll_outdiv should be selected according to the desired output f out , as described in table 67. t he divider, fll_outdiv, must be set so that f vco is in the range 90-100mhz. output frequency f out fll_outdiv 2.8125 mhz - 3.125 mhz 4h (divide by 32) 5.625 mhz - 6.25 mhz 3h (divide by 16) 11.25 mhz - 12.5 mhz 2h (divide by 8) 22.5 mhz - 25 mhz 1h (divide by 4) table 67 selection of fll_outdiv the value of fll_fratio should be selected as described in table 68. reference frequency f ref fll_fratio 1mhz - 13.5mhz 0h (divide by 1) 256khz - 1mhz 1h (divide by 2) 128khz - 256khz 2h (divide by 4) 64khz - 128khz 3h (divide by 8) less than 64khz 4h (divide by 16) table 68 selection of fll_fratio in order to determine the remaining fll parameters, the fll operating frequency, f vco , must be calculated, as given by the following equation: f vco = (f out x fll_outdiv) the value of fll_n and fll_k can then be determined as follows: n.k = f vco / (fll_fratio x f ref ) see table 69 for the coding of t he fll_outdiv and fll_fratio fields.
production data WM8903 w pd, rev 4.5, june 2012 103 note that f ref is the input frequency, after division by fll_clk_ref_div, where applicable. in fll fractional mode, the fractional portion of the n.k multiplier is held in the fll_k register field. this field is coded as a fixed poi nt quantity, where the msb has a weighting of 0.5. note that, if desired, the value of this field may be calculated by multiplying k by 2 16 and treating fll_k as an integer value, as illustrated in the following example: if n.k = 8.192, then k = 0.192 multiplying k by 2 16 gives 0.192 x 65536 = 12582.912 (decimal) apply rounding to the nearest integer = 12583 (decimal) = 3127 (hex) for best performance, fll fractional mode should always be used. ther efore, if the calculations yield an integer value of n.k, then it is reco mmended to adjust fll_fratio in order to obtain a non- integer value of n.k. care must always be taken to ensure that the fll operating frequency, f vco , is within its recommended limits of 90-100 mhz. the register fields that control the fll are descr ibed in table 69. example settings for a variety of reference frequencies and output frequencies are shown in table 70. register address bit label default description r128 (80h) fll control 1 7:4 fll_gain [3:0] 0h gain applied to error 0000 = x 1 (recommended value) 0001 = x 2 0010 = x 4 0011 = x 8 0100 = x 16 0101 = x 32 0110 = x 64 0111 = x 128 1000 = x 256 recommended that this register is not changed from default. 3 fll_hold 0 fll hold select 0 = disabled 1 = enabled this feature enables free-running mode in fll when reference clock is removed 2 fll_frac 0 fractional enable 0 = integer mode 1 = fractional mode fractional mode is recommended in all cases 0 fll_ena 0 fll enable 0 = disabled 1 = enabled r129 (81h) fll control 2 12:11 fll_clk_src [1:0] 00 fll clock source 00 = mclk 01 = bclk 10 = lrc 11 = reserved
WM8903 production data w pd, rev 4.5, june 2012 104 register address bit label default description 10:9 fll_clk_ref _div [1:0] 00 fll clock reference divider 00 = mclk / 1 01 = mclk / 2 10 = mclk / 4 11 = mclk / 8 mclk (or other input reference) must be divided down to <=13.5mhz. for lower power operation, the reference clock can be divided down further if desired. 8:6 fll_ctrl_ra te [2:0] 000 frequency of the fll control block 000 = f vco / 1 (recommended value) 001 = f vco / 2 010 = f vco / 3 011 = f vco / 4 100 = f vco / 5 101 = f vco / 6 110 = f vco / 7 111 = f vco / 8 recommended that this register is not changed from default. 5:3 fll_outdiv [2:0] 000 f out clock divider 000 = 2 001 = 4 010 = 8 011 = 16 100 = 32 101 = 64 110 = 128 111 = 256 (f out = f vco / fll_outdiv) 2:0 fll_fratio [2:0] 000 f vco clock divider 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 1xx = divide by 16 000 recommended for f ref > 1mhz 100 recommended for f ref < 64khz r130 (82h) fll control 3 15:0 fll_k [15:0] 0000h fractional multiply for f ref (msb = 0.5) r131 (83h) fll control 4 9:0 fll_n [9:0] 000h integer multiply for f ref (lsb = 1) table 69 fll register map
production data WM8903 w pd, rev 4.5, june 2012 105 free-running fll clock the fll can generate a clock signal even when the ex ternal reference is removed. it should be noted that the accuracy of this clock is reduced, and a reference source should always be used where possible. in free-running modes, the fll is not suffi ciently accurate for hi-fi audio applications. the free-running modes are suitable for clocking other functions, including the write sequencer and dc servo control. the free-running mode can be us ed to support the analogue input (bypass) audio paths. a clock reference is required for initial configur ation of the fll as described above. for free-running operation, the fll_hold bit should be set, as de scribed in table 69. when fll_hold is set, the fll will continue to generate a stable output cl ock after the reference input is stopped or disconnected. note that the fll must be selected as the clk_sys source by setting clk_src_sel (see table 61). note that, in the absence of any reference cl ock, the fll output is subject to a very wide tolerance. see ?electrical characterist ics? for details of the fll accuracy. gpio outputs from fll the WM8903 has an internal signal which indicate s whether the fll lock has been achieved. the fll lock status is an input to the interrupt contro l circuit and can be used to trigger an interrupt event - see ?interrupts?. the fll lock signal can be output directly on a gpio pin as an external indication of fll lock. see ?general purpose input/output (gpio)? for details of how to configure a gpio pin to output the fll lock signal. the fll clock can be output directly on a gpio pin as a clock signal for other circuits. note that the fll clock may be output even if the fll is not selected as the WM8903 clk_sys source. the clocking configuration is illustrated in figure 55. see ?general purpose input/output (gpio)? for details of how to configure a gpio pin to output the fll clock. example fll calculation to generate 12.288 mhz output (f out ) from a 12.000 mhz reference clock (f ref ): ? set fll_clk_ref_div in order to generate f ref <=13.5mhz: fll_clk_ref_div = 00 (divide by 1) ? set fll_ctrl_rate to the recommended setting: fll_ctrl_rate = 000 (divide by 1) ? set fll_gain to the recommended setting: fll_gain = 0000 (multiply by 1) ? set fll_outdiv for the required output frequency as shown in table 67:- f out = 12.288 mhz, therefore fll_outdiv = 2h (divide by 8) ? set fll_fratio for the given refer ence frequency as shown in table 68: f ref = 12mhz, therefore fll_fratio = 0h (divide by 1) ? calculate f vco as given by f vco = f out x fll_outdiv:- f vco = 12.288 x 8 = 98.304mhz ? calculate n.k as given by n.k = f vco / (fll_fratio x f ref ): n.k = 98.304 / (1 x 12) = 8.192 ? determine fll_n and fll_k from the in teger and fractional portions of n.k:- fll_n is 8. fll_k is 0.192 ? confirm that n.k is a fractional quantity and set fll_frac: n.k is fractional. set fll_frac = 1. note that, if n.k is an integer, then an alternative value of fll_fratio should be selected in order to produce a fractional value of n.k.
WM8903 production data w pd, rev 4.5, june 2012 106 example fll settings table 70 provides example fll settings for generating common clk_sys frequencies from a variety of low and high frequency reference inputs. f ref f out fll_clk_ ref_div f vco fll_n fll_k fll_ fratio fll_ outdiv fll_ frac 32.000 khz 12.288 mhz divide by 1 (0h) 98.304 mhz 192 (0c0h) 0 (0000h) 16 (4h) 8 (2h) 0 32.000 khz 11.2896 mhz divide by 1 (0h) 90.3168 mhz 176 (0b0h) 0.4 (6666h) 16 (4h) 8 (2h) 1 32.768 khz 12.288 mhz divide by 1 (0h) 98.304 mhz 187 (0bbh) 0.5 (8000h) 16 (4h) 8 (2h) 1 32.768 khz 11.288576 mhz divide by 1 (0h) 90.3086 mhz 172 (0ach) 0.25 (4000h) 16 (4h) 8 (2h) 1 32.768 khz 11.2896 mhz divide by 1 (0h) 90.3168 mhz 172 (0ach) 0.2656 (4400h) 16 (4h) 8 (2h) 1 48 khz 12.288 mhz divide by 1 (0h) 98.304 mhz 128 (080h) 0 (0000h) 16 (4h) 8 (2h) 0 11.3636 mhz 12.368544 mhz divide by 1 (0h) 98.9484 mhz 8 (008h) 0.707483 (b51eh) 1 (0h) 8 (2h) 1 12.000 mhz 12.288 mhz divide by 1 (0h) 98.304 mhz 8 (008h) 0.192 (3127h) 1 (0h) 8 (2h) 1 12.000 mhz 11.289597 mhz divide by 1 (0h) 90.3168 mhz 7 (007h) 0.526398 (86c2h) 1 (0h) 8 (2h) 1 12.288 mhz 12.288 mhz divide by 1 (0h) 98.304 mhz 8 (008h) 0 (0000h) 1 (0h) 8 (2h) 0 12.288 mhz 11.2896 mhz divide by 1 (0h) 90.3168 mhz 7 (007h) 0.35 (599ah) 1 (0h) 8 (2h) 1 13.000 mhz 12.287990 mhz divide by 1 (0h) 98.3039 mhz 7 (007h) 0.56184 (8fd5h) 1 (0h) 8 (2h) 1 13.000 mhz 11.289606 mhz divide by 1 (0h) 90.3168 mhz 6 (006h) 0.94745 (f28ch) 1 (0h) 8 (2h) 1 19.200 mhz 12.287988 mhz divide by 2 (1h) 98.3039 mhz 10 (00ah) 0.23999 (3d70h) 1 (0h) 8 (2h) 1 19.200 mhz 11.289588 mhz divide by 2 (1h) 90.3167 mhz 9 (009h) 0.40799 (6872h) 1 (0h) 8 (2h) 1 table 70 example fll settings
production data WM8903 w pd, rev 4.5, june 2012 107 general purpose input/output (gpio) the WM8903 provides five multi- function pins which can be conf igured to provide a number of different functions. these are digi tal input/output pins on the dbv dd power domain. the gpio pins are: ? gpio1/dmic_lr ? gpio2/dmic_dat ? gpio3/addr ? interrupt (gpio4) ? bclk (gpio5) each general purpose i/o pin can be configured to be a gpio input or configured as one of a number of output functions. signal de-bounci ng can be selected on gpio input pins for use with jack/button detect applications. table 71 lists t he functions that are available on each of these pins. the default function is highlighted for each pin. gpio pins gpio pin function gpio1/d mic_lr gpio2/d mic_dat gpio3/ addr interrupt (gpio4) bclk (gpio5) gpio output yes yes yes yes yes bclk input/output no no no no yes interrupt output (irq) yes yes yes yes yes digital microphone clock (dmic_lr) yes no no no no digital microphone data (dmic_dat) no yes no no no gpio input (including jack/button detect) yes yes yes yes yes micbias current detect output yes yes yes yes yes micbias short circuit detect output yes yes yes yes yes fll lock output yes yes yes yes yes fll clock output yes yes yes yes yes table 71 gpio functions available the register fields that control the functionality of these pins are described in table 72. for each pin, the selected function is determined by the gpn_fn fiel d, where n identifies the gpio pin (1 to 5). note that the interrupt pin is also referred to as gpio4; the bclk pin is also referred to as gpio5. the pin direction, set by gpn_dir, must be set according to the function selected by gpn_fn. the characteristics of any pin selected as an output may be controlled by setting gpn_op_cfg - an output pin may be either cmos or open-drain. when a pin is configured as a gpio output, its level can be set to logic 0 or logi c 1 using the gpn_lvl field. a pin configured as a gpio input can be used to trigger an interrupt event. this input may be configured as active high or acti ve low using the gpn_ip_cfg field. de-bouncing of this input may be enabled using the gpn_db field. internal pull- up and pull-down resistors may be enabled using the gpn_pu and gpn_pd fields. (note t hat if gpn_pu and gpn_pd are both set for any gpio pin, then the pull-up and pull-down will be disabled.) each of the gpio pins is an input to the interrupt control circuit and can be us ed to trigger an interrupt event. the register field gpn_intmode selects edge detect or level detect interrupt functionality. edge detect raises an interrupt on rising and falling tr ansitions. level detect asserts the interrupt for as long as the gpio status is asserted. see ?interrupts?.
WM8903 production data w pd, rev 4.5, june 2012 108 the digital microphone interface and micbias curr ent detect functions are described in the ?analogue input signal path? section. interrupt output is the default function of gp io4. see ?interrupts? for further details. bclk is the default function of gpio5. this may be input or output. note that, when bclk is enabled on this pin (gp5_fn = 1h), the other gpio control fi elds for this pin have no effect. when bclk is not enabled on this pin (gp5_fn 1h), the WM8903 uses the mclk input as the bit clock. see ?digital audio interface control? for further details. register address bit label default description r116 (74h) gpio control 1 13:8 gp1_fn [5:0] 00_0000 gpio 1 pin function select 00h = gpio output 01h = reserved 02h = irq output 03h = gpio input 04h = micbias current detect 05h = micbias short circuit detect 06h = dmic_lr clock output 07h = reserved 08h = fll lock output 09h = fll clock output 0ah to 3fh = reserved 7 gp1_dir 1 gpio pin direction 0 = output 1 = input 6 gp1_op_cfg 0 output pin configuration 0 = cmos 1 = open-drain 5 gp1_ip_cfg 1 input pin configuration 0 = active low 1 = active high 4 gp1_lvl 0 gpio output level (when gp1_fn = 00000) 0 = logic 0 1 = logic 1 3 gp1_pd 1 gpio pull-down enable 0 = pull-down disabled 1 = pull-down enabled (approx 100k ? ) 2 gp1_pu 0 gpio pull-up enable 0 = pull-up disabled 1 = pull-up enabled (approx 100k ? ) 1 gp1_intmode 0 gpio interrupt mode 0 = level triggered 1 = edge triggered 0 gp1_db 0 gpio de-bounce 0 = gpio is not debounced 1 = gpio is debounced
production data WM8903 w pd, rev 4.5, june 2012 109 register address bit label default description r117 (75h) gpio control 2 13:8 gp2_fn [5:0] 00_0000 gpio 2 pin function select 00h = gpio output 01h = reserved 02h = irq output 03h = gpio input 04h = micbias current detect 05h = micbias short circuit detect 06h = dmic_dat data input 07h = reserved 08h = fll lock output 09h = fll clock output 0ah to 3fh = reserved 7 gp2_dir 1 gpio pin direction 0 = output 1 = input 6 gp2_op_cfg 0 output pin configuration 0 = cmos 1 = open-drain 5 gp2_ip_cfg 1 input pin configuration 0 = active low 1 = active high 4 gp2_lvl 0 gpio output level (when gp2_fn = 00000) 0 = logic 0 1 = logic 1 3 gp2_pd 1 gpio pull-down enable 0 = pull-down disabled 1 = pull-down enabled (approx 100k ? ) 2 gp2_pu 0 gpio pull-up enable 0 = pull-up disabled 1 = pull-up enabled (approx 100k ? ) 1 gp2_intmode 0 gpio interrupt mode 0 = level triggered 1 = edge triggered 0 gp2_db 0 gpio de-bounce 0 = gpio is not debounced 1 = gpio is debounced r118 (76h) gpio control 3 13:8 gp3_fn [5:0] 00_0000 gpio 3 pin function select 00h = gpio output 01h = reserved 02h = irq output 03h = gpio input 04h = micbias current detect 05h = micbias short circuit detect 06h = reserved 07h = reserved 08h = fll lock output 09h = fll clock output 0ah to 3fh = reserved 7 gp3_dir 1 gpio pin direction 0 = output 1 = input
WM8903 production data w pd, rev 4.5, june 2012 110 register address bit label default description 6 gp3_op_cfg 0 output pin configuration 0 = cmos 1 = open-drain 5 gp3_ip_cfg 1 input pin configuration 0 = active low 1 = active high 4 gp3_lvl 0 gpio output level (when gp3_fn = 00000) 0 = logic 0 1 = logic 1 3 gp3_pd 1 gpio pull-down enable 0 = pull-down disabled 1 = pull-down enabled (approx 100k ? ) 2 gp3_pu 0 gpio pull-up enable 0 = pull-up disabled 1 = pull-up enabled (approx 100k ? ) 1 gp3_intmode 0 gpio interrupt mode 0 = level triggered 1 = edge triggered 0 gp3_db 0 gpio de-bounce 0 = gpio is not debounced 1 = gpio is debounced r119 (77h) gpio control 4 13:8 gp4_fn [5:0] 00_0010 gpio 4 pin function select 00h = gpio output 01h = reserved 02h = irq output 03h = gpio input 04h = micbias current detect 05h = micbias short circuit detect 06h = reserved 07h = reserved 08h = fll lock output 09h = fll clock output 0ah to 3fh = reserved 7 gp4_dir 0 gpio pin direction 0 = output 1 = input 6 gp4_op_cfg 0 output pin configuration 0 = cmos 1 = open-drain 5 gp4_ip_cfg 1 input pin configuration 0 = active low 1 = active high 4 gp4_lvl 0 gpio output level (when gp4_fn = 00000) 0 = logic 0 1 = logic 1 3 gp4_pd 0 gpio pull-down enable 0 = pull-down disabled 1 = pull-down enabled (approx 100k ? )
production data WM8903 w pd, rev 4.5, june 2012 111 register address bit label default description 2 gp4_pu 0 gpio pull-up enable 0 = pull-up disabled 1 = pull-up enabled (approx 100k ? ) 1 gp4_intmode 0 gpio interrupt mode 0 = level triggered 1 = edge triggered 0 gp4_db 0 gpio de-bounce 0 = gpio is not debounced 1 = gpio is debounced r120 (78h) gpio control 5 13:8 gp5_fn [5:0] 00_0001 gpio 5 pin function select 00h = gpio output 01h = bclk 02h = irq output 03h = gpio input 04h = micbias current detect 05h = micbias short circuit detect 06h = reserved 07h = reserved 08h = fll lock output 09h = fll clock output 0ah to 3fh = reserved 7 gp5_dir 1 gpio pin direction 0 = output 1 = input 6 gp5_op_cfg 0 output pin configuration 0 = cmos 1 = open-drain 5 gp5_ip_cfg 1 input pin configuration 0 = active low 1 = active high 4 gp5_lvl 0 gpio output level (when gp5_fn = 00000) 0 = logic 0 1 = logic 1 3 gp5_pd 0 gpio pull-down enable 0 = pull-down disabled 1 = pull-down enabled (approx 100k ? ) 2 gp5_pu 0 gpio pull-up enable 0 = pull-up disabled 1 = pull-up enabled (approx 100k ? ) 1 gp5_intmode 0 gpio interrupt mode 0 = level triggered 1 = edge triggered 0 gp5_db 0 gpio de-bounce 0 = gpio is not debounced 1 = gpio is debounced table 72 gpio control
WM8903 production data w pd, rev 4.5, june 2012 112 interrupts the interrupt controller has multiple inputs. t hese include the gpio input pins and the micbias current detection circuits. any comb ination of these inputs can be us ed to trigger an interrupt (irq) event. there is an interrupt status field associated with each of the irq inputs. these are contained in the interrupt status register (r121), as described in table 73. the status of the irq inputs can be read from this register at any time, or else in res ponse to the interrupt output being signalled via a gpio pin. the interrupt output represents the logical ?or? of all the unmasked irq inputs. the bits within the interrupt status register (r121) are latching fields and, once they are set, they are not reset until the status register is read. accordingly, the interrupt output is not reset until each of the unmasked irq inputs has been read. note that, if the condition that caused the irq input to be asserted is still valid, then the interrupt output will remain set even after the status register has been read. each of the irq inputs can be individually masked or enabled as an input to the interrupt function, using the bits contained in the interrupt status ma sk register (r122). note that the interrupt status fields remain valid, even when masked, but the mask ed bits will not cause the interrupt output to be asserted. when a gpio input is used as in terrupt event, the polarity can be set using gp_ip_cfg as described in table 72. the polarity of the micbias det ection functions can be set using micdet_inv and micshrt_inv as described in table 73; this allows the irq event to be used to indicate either the removal or insertion of a microphone accessory. t he polarity of the fll lock indication can be set using fll_lock_inv; this allows the irq event to be used to indicate either the fll lock or the fll not-locked status. by default, the interrupt output is active hi gh. the polarity can be inverted using irq_pol. the interrupt output may be configured the interrupt/gpio4 pin or on the gpio1/dmic_lr, gpio2/dmic_dat, gpio3/addr or bclk/gpio5 pins. interrupt output is the default function on the interrupt pin (gp4_fn = 2h), but the interrup t pin can also be used to support other functions. see ?general purpose inpu t/output (gpio)? for details of how to configure gpio pins for interrupt (irq) output. the WM8903 interrupt controller circuit is illustrated in figure 54. the associated control fields are described in table 73. micshrt_inv micdet_inv micshrt_eint micdet_eint wseq_busy_eint im_micshrt_eint im_micdet_eint im_wseq_busy_eint interrupt im_gp5_eint gp5_eint gp4_eint gp3_eint gp2_eint im_gp4_eint im_gp3_eint im_gp2_eint gp1_eint im_gp1_eint mic_short_irq mic_detect_irq wseq_busy_irq gpio5_irq gpio4_irq gpio3_irq gpio2_irq gpio1_irq irq_pol fll_lock_inv fll_lock_eint im_fll_lock_eint fll_lock_irq status register latches read only; cleared on register read figure 56 interrupt controller
production data WM8903 w pd, rev 4.5, june 2012 113 register address bit label default description r121 (79h) interrupt status 1 15 micshrt_eint 0 micbias short circuit detect irq status 0 = short circuit current irq not set 1 = short circuit current irq set (read-only register) 14 micdet_eint 0 micbias current detect irq status 0 = current detect irq not set 1 = current detect irq set (read-only register) 13 wseq_busy_e int 0 write sequencer busy irq status 0 = wseq irq not set 1 = wseq irq set the write sequencer asserts this flag when it has completed a programmed sequence - ie it indicates that the write sequencer is not busy. (read-only register) 5 fll_lock_ein t 0 fll lock irq status 0 = fll lock irq not set 1 = fll lock irq set (read-only register) 4 gp5_eint 0 gpio5 irq status 0 = gpio5 irq not set 1 = gpio5 irq set (read-only register) 3 gp4_eint 0 gpio4 irq status 0 = gpio4 irq not set 1 = gpio4 irq set (read-only register) 2 gp3_eint 0 gpio3/addr irq status 0 = gpio3 irq not set 1 = gpio3 irq set (read-only register) 1 gp2_eint 0 gpio2/dmic_dat irq status 0 = gpio2 irq not set 1 = gpio2 irq set (read-only register) 0 gp1_eint 0 gpio1/dmic_lr irq status 0 = gpio1 irq not set 1 = gpio1 irq set (read-only register) r122 (7ah) interrupt status 1 mask 15 im_micshrt_e int 1 interrupt mask for micbias short circuit detect 0 = not masked 1 = masked 14 im_micdet_ei nt 1 interrupt mask for micbias current detect 0 = not masked 1 = masked 13 im_wseq_bus y_eint 1 interrupt mask for wseq busy indication 0 = not masked 1 = masked
WM8903 production data w pd, rev 4.5, june 2012 114 register address bit label default description 5 im_fll_lock_ eint 1 interrupt mask for fll lock 0 = not masked 1 = masked 4 im_gp5_eint 1 interrupt mask for gpio5 0 = not masked 1 = masked 3 im_gp4_eint 1 interrupt mask for gpio4 0 = not masked 1 = masked 2 im_gp3_eint 1 interrupt mask for gpio3/addr 0 = not masked 1 = masked 1 im_gp2_eint 1 interrupt mask for gpio2/dmic_dat 0 = not masked 1 = masked 0 im_gp1_eint 1 interrupt mask for gpio1/dmic_lr 0 = not masked 1 = masked r123 (7bh) interrupt polarity 1 15 micshrt_inv 0 micbias short circuit detect polarity 0 = detect current increase above threshold 1 = detect current decrease below threshold 14 micdet_inv 0 micbias current detect polarity 0 = detect current increase above threshold 1 = detect current decrease below threshold 5 fll_lock_inv 0 fll lock polarity 0 = non-inverted 1 = inverted r126 (7eh) interrupt control 0 irq_pol 0 interrupt output polarity 0 = active high 1 = active low table 73 interrupt control
production data WM8903 w pd, rev 4.5, june 2012 115 control interface the WM8903 is controlled by writing to registers thr ough a 2-wire serial control interface. readback is available for all registers, including chip id, power management status and gpio status. note that, if it cannot be assured that mclk is pr esent when accessing the register map, then it is required to set clk_sys_ena = 0 to ensure correct operation. see ?clocking and sample rates? for further details and for the definition of clk_sys_ena. the WM8903 is a slave device on the control interface; sclk is a clock input, while sdin is a bi- directional data pin. to allow arbitration of multip le slaves (and/or multip le masters) on the same interface, the WM8903 transmits logic 1 by tri-stati ng the sdin pin, rather than pulling it high. an external pull-up resistor is requir ed to pull the sdin line high so that the logic 1 can be recognised by the master. in order to allow many devices to share a singl e 2-wire control bus, ever y device on the bus has a unique 8-bit device id (this is not the same as t he 8-bit address of each register in the WM8903). the default device id for the WM8903 is 0011 0100 (34h). the lsb of the device id is the read/write bit; this bit is set to logic 1 fo r ?read? and logic 0 for ?write?. alternatively, the device id can be set to 0011 0110 (0x36) by pulling the gpio3/addr pin high during device start-up, when the internal power- on reset signal porb (see ?power-on reset?) is released. the setup and hold times for device id sele ction are shown in table 74. after the device id has been selected, the gpio3/a ddr pin can be used as a gpio. symbol min typ max unit t pusetup 100 s t puhold 100 s table 74 gpio3/addr latch on power-up timing the WM8903 operates as a slave device only. the controller indicates the start of data transfer with a high to low transition on sdin while sclk remains high. this indicates that a device id, register address and data will follow. the WM8903 responds to t he start condition and shifts in the next eight bits on sdin (8-bit device id, including read/write bit, msb first). if the dev ice id received matches the device id of the WM8903, then the WM8903 responds by pulling sdin low on the next clock pulse (ack). if the device id is not recognised or the r/w bit is ?1? when operating in write only mode, the WM8903 returns to the idle condition and waits for a new start condition and valid address. if the device id matches the device id of the WM8903, the data transfer continues as described below. the controller indicates the end of data trans fer with a low to high transition on sdin while sclk remains high. after receiving a complete address and data sequence the WM8903 returns to the idle state and waits for another start condition. if a start or stop condition is detected out of sequence at any point during data transfer (i.e. sdin changes while sclk is high), the device returns to the idle condition. the WM8903 supports the following read and write operations: ? single write ? single read ? multiple write using auto-increment ? multiple read using auto-increment the sequence of signals associated with a single regi ster write operation is illustrated in figure 57.
WM8903 production data w pd, rev 4.5, june 2012 116 figure 57 control interface register write the sequence of signals associated with a single regi ster read operation is illustrated in figure 58. figure 58 control interface register read the control interface also supports other register operations, as listed above. the interface protocol for these operations is summarised below. the terminology used in the following figures is detailed in table 75. note that multiple write and multiple read operat ions are supported using the auto-increment mode. this feature enables the host processor to access sequential blocks of the data in the WM8903 register map faster than is possibl e with single register operations. terminology description s start condition sr repeated start a acknowledge (sdin low) a not acknowledge (sdin high) p stop condition r/w readnotwrite 0 = write 1 = read [white field] data flow from bus master to WM8903 [grey field] data flow from WM8903 to bus master table 75 control interface terminology figure 59 single register write to specified address
production data WM8903 w pd, rev 4.5, june 2012 117 figure 60 single register read from specified address figure 61 multiple register write to specified address using auto-increment sr s a register address (0) a a (1) read from 'register address' msbyte data 0 lsbyte data 0 a a p msbyte data n lsbyte data n a a a msbyte data n-1 lsbyte data n-1 a a read from 'last register address+n' read from 'last register address+n-1' device id rw device id rw figure 62 multiple register read from specified address using auto-increment figure 63 multiple register read from last address using auto-increment
WM8903 production data w pd, rev 4.5, june 2012 118 control write sequencer the control write sequencer is a programmable unit that forms part of the WM8903 control interface logic. it provides the ability to perform a sequence of register write operations with the minimum of demands on the host processor - the sequence may be initiated by a single operation from the host processor and then left to execute independently. default sequences for start-up and shut-down are provided (see ?default s equences? section). it is recommended that these default sequences ar e used unless changes become necessary. when a sequence is initiated, the sequencer performs a series of pre-defined register writes. the host processor informs the sequencer of the st art index of the required sequence within the sequencer?s memory. at each step of the sequence, t he contents of the selected register fields are read from the sequencer?s memory and copied into the WM8903 control registers. this continues sequentially through the sequencer?s memory until an ?end of sequence? bit is encountered; at this point, the sequencer stops and an interrupt status flag is asserted. for cases where the timing of the write sequence is important, a programmable delay c an be set for specific steps within the sequence. note that the control write sequencer?s internal clo ck is derived from the internal clock clk_sys. an external mclk signal must be present when usi ng the control write sequencer, and clk_sys must be enabled by setting clk_sys_ena (see ?clocking and sample rates?). the clock division from mclk is handled transparently by the WM8903 without user intervention, as long as mclk and sample rates are set correctly. initiating a sequence the register fields associated with running the control write sequencer are described in table 76. the write sequencer clock is enabled by setting the wsmd_clk_ena bit. note that the operation of the control write sequencer also requires the internal clock clk_sys to be enabled via the clk_sys_ena (see ?clocking and sample rates?). the start index of the required sequence must be written to the wseq_start_index field. setting the wseq_start bit initiates the sequencer at the given start index. the write sequencer can be interrupted by wr iting a logic 1 to the wseq_abort bit. the current status of the write sequencer can be r ead using two further register fields - when the wseq_busy bit is asserted, this indicates that the write sequencer is busy. note that, whilst the control write sequencer is running a sequence (indicated by the wseq_busy bit), normal read/write operations to the control registers cannot be supported. (the write sequencer registers and the software reset register can still be access ed when the sequencer is busy.) the index of the current step in the write sequencer can be read fr om the wseq_current_index field; this is an indicator of the sequencer?s progress. on completion of a sequence, this field holds the index of the last step within the last commanded sequence. when the write sequencer reaches the end of a sequenc e, it asserts the wseq_busy_eint flag in register r121 (see table 73 within the ?interrupt s? section). this flag can be used to generate an interrupt event on completion of the sequence. note that the wseq_busy_eint flag is asserted to indicate that the wseq is not busy.
production data WM8903 w pd, rev 4.5, june 2012 119 register address bit label default description r108 (6ch) write sequencer 0 8 wsmd_clk_en a 0 write sequencer / mic detect clock enable. 0 = disabled 1 = enabled r111 (6fh) write sequencer 3 9 wseq_abort 0 writing a 1 to this bit aborts the current sequence and returns control of the device back to the serial control interface. (write-only register) 8 wseq_start 0 writing a 1 to this bit starts the write sequencer at the memory location indicated by the wseq_start_index field. the sequence continues until it reaches an ?end of sequence? flag. at the end of the sequence, this bit will be reset by the write sequencer. (write-only register) 5:0 wseq_start_ index [5:0] 00_0000 sequence start index. this is the memory location of the first command in the selected sequence. 0 to 31 = ram addresses 32 to 48 = rom addresses 49 to 63 = reserved r112 (70h) write sequencer 4 9:4 wseq_curre nt_index [5:0] 00_0000 sequence current index. this is the location of the most recently accessed command in the write sequencer memory. (read-only register) 0 wseq_busy 0 sequencer busy flag 0 = sequencer idle 1 = sequencer busy note: it is not possible to write to control registers via the control interface while the sequencer is busy. (read-only register) table 76 write sequencer control ? initiating a sequence programming a sequence a sequence consists of write operations to data bits (or groups of bits ) within the control registers. the register fields associated with programming the control write sequencer are described in table 77. for each step of the sequence being programmed, the sequencer index must be written to the wseq_write_index field. the values 0 to 31 correspond to all the available ram addresses within the write sequencer memory. (note that memory addresses 32 to 48 also exist, but these are rom addresses, which are not programmable.) having set the index as described above, register r109 must be written to (containing the control register address, the start bit position and the fi eld width applicable to this step of the sequence). also, register r110 must be written to (containi ng the register data, the end of sequence flag and the delay time required after this step is executed). after writing to these two registers, the next step in the sequence may be programmed by updat ing wseq_write_index and repeating the procedure.
WM8903 production data w pd, rev 4.5, june 2012 120 wseq_addr is an 8-bit field contai ning the control register address in which the data should be written. wseq_data_start is a 4-bit field which identifie s the lsb position within the selected control register to which the data should be written. setting wseq_data_start = 0100 will cause 1-bit data to be written to bit 4. with this setting, 4-bit data would be written to bits 7:4 and so on. wseq_data_width is a 3-bit field which identifies the width of the data block to be written. this enables selected portions of a control register to be updated without any concern for other bits within the same register, eliminating the need for read-modi fy-write procedures. values of 0 to 7 correspond to data widths of 1 to 8 respectively. for ex ample, setting wseq_data_width = 010 will cause a 3-bit data block to be written. note that the maxi mum value of this field corresponds to an 8-bit data block; writing to register fields greater t han 8 bits wide must be performed using two separate operations of the control write sequencer. wseq_data is an 8-bit field which contains the data to be written to the selected control register. the wseq_data_width field determines how many of these bits are written to the selected register; the most significant bi ts (above the number indicated by wseq_data_width) are ignored. wseq_delay is a 4-bit field which controls t he waiting time between the current step and the next step in the sequence. the total delay time per step (including execut ion) is given by: t = k (2 wseq_delay + 8) where k = 62.5 ? s (under recommended operating conditions) this gives a useful range of execution/delay times from 562 ? s up to 2.048s per step. wseq_eos is a 1-bit field which indicates the end of sequence. if this bit is set, then the control write sequencer will automatically stop after this step has been executed. register address bit label default description r108 (6ch) write sequencer 0 4:0 wseq_writ e_index [4:0] 0_0000 sequence write index. this is the memory location to which any updates to r109 and r110 will be copied. 0 to 31 = ram addresses r109 (6dh) write sequencer 1 14:12 wseq_data _width [2:0] 000 width of the data block written in this sequence step. 000 = 1 bit 001 = 2 bits 010 = 3 bits 011 = 4 bits 100 = 5 bits 101 = 6 bits 110 = 7 bits 111 = 8 bits 11:8 wseq_data _start [3:0] 0000 bit position of the lsb of the data block written in this sequence step. 0000 = bit 0 ? 1111 = bit 15 7:0 wseq_addr [7:0] 0000_0000 control register address to be written to in this sequence step. r110 (6eh) write sequencer 2 14 wseq_eos 0 end of sequence flag. this bit indicates whether the control write sequencer should stop after executing this step. 0 = not end of sequence 1 = end of sequence (stop the sequencer after this step). 11:8 wseq_dela y [3:0] 0000 time delay after executing this step. total time per step (including execution) = 62.5s (2 wseq_delay + 8)
production data WM8903 w pd, rev 4.5, june 2012 121 register address bit label default description 7:0 wseq_data [7:0] 0000_0000 data to be written in this sequence step. when the data width is less than 8 bits, then one or more of the msbs of wseq_data are ignored. it is recommended that unused bits be set to 0. table 77 write sequencer control - programming a sequence note that a ?dummy? write can be inserted into a control sequence by commanding the sequencer to write a value of 0 to bit 0 of register r255 (ffh). th is is effectively a write to a non-existent register location. this can be used in order to create pl aceholders ready for easy adaptation of the sequence. for example, a sequence could be defined to power-up a mono signal path from dacl to headphone, with a ?dummy? write included to leave spac e for easy modification to a stereo signal path configuration. dummy writes can also be used in order to implement additional time delays between register writes. dummy writes are included in the default start-up sequence ? see table 79. in summary, the control register to be written is set by the wseq_addr field. the data bits that are written are determined by a combination of wseq_data_start, wseq_data_width and wseq_data. this is illustrated below for an example case of writing to the vmid_res field within register r5 (05h). in this example, the start position is bit 01 (wseq_data_start = 0001b) and the data width is 2 bits (wseq_data_width = 0001b). with these settings, the control write sequencer would updated the control register r5 [2:1] with the contents of wseq_data [1:0]. b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 r5 (05h) vmid control 0 lsb position = b01 wseq_data_start n = 0001 data width = 2 bits wseq_data_width n = 0001 wseq_data n (8 bits) b07 b06 b05 b04 b03 b02 b01 b00 wseq_data_width n = 2 bits. therefore, only the least significant 2 bits are valid. bits 02 to 07 are discarded vmid_res figure 64 control write sequencer example
WM8903 production data w pd, rev 4.5, june 2012 122 default sequences when the WM8903 is powered up, two control wr ite sequences are available through default settings in both ram and rom memory locations. the purpose of these sequences, and the register write required to initiate them, is summarised in t able 78. in both cases, a single register write will initiate the sequence. wseq start index wseq finish index purpose to initiate 0 (00h) 29 (1dh) start-up sequence write 0100h to register r111 (6fh) 32 (20h) 48 (30h) shutdown sequence write 0120h to register r111 (6fh) table 78 write sequencer default sequences note on shut-down sequence: the instruction at index address 32 (20h) shorts the outputs lineoutl and lineoutr. if the line outputs are not in use at the time the sequence is run, then the sequence could, instead, be started at index address 33. index addresses 0 to 31 may be programmed to user s? own settings at any time, as described in ?programming a sequence? users? ow n settings remain in memory and are not affected by software resets (i.e. writing to register r0). however, any non-default sequences are lost when the device is powered down. start-up sequence the start-up sequence is initiated by writing 0100h to register r111 (6fh). this single operation starts the control write sequencer at index addr ess 0 (00h) and executes the sequence defined in table 79. for typical clocking configurations with mclk =12.288mhz, this sequence takes approximately 425ms to run. wseq index register address width start data delay eos description 0 (00h) r4 (04h) 5 bits bit 0 1ah 0h 0b pobctrl = 1 isel [1:0] = 10b startup_bias_ena = 1 bias_ena = 0 (delay = 0.5625ms) 1 (01h) r65 (41h) 1 bit bit 1 01h 9h 0b spk_discharge = 1 (delay = 32.5ms) 2 (02h) r17 (11h) 2 bits bit 0 03h 0h 0b spkl_ena = 1 spkr_ena = 1 (delay = 0.5625ms) 3 (03h) r65 (41h) 1 bit bit 1 00h 0h 0b spk_discharge = 0 (delay = 0.5625ms) 4 (04h) r5 (5h) 8 bits bit 0 f7h bh 0b vmid_tie_ena = 1 bufio_ena = 1 vmid_io_ena = 1 vmid_soft = 10 vmid_res = 11 vmid_buf_ena = 1 (delay = 128.5ms) 5 (05h) r17 (11h) 2 bits bit 0 00h 0h 0b spkl_ena = 0 spkr_ena = 0 (delay = 0.5625ms)
production data WM8903 w pd, rev 4.5, june 2012 123 wseq index register address width start data delay eos description 6 (06h) r5 (5h) 2 bits bit 3 00h 0h 0b vmid_soft = 00 (delay = 0.5625ms) 7 (07h) r5 (05h) 2 bits bit 1 01h 0h 0b vmid_res [1:0] = 01b (delay = 0.5625ms) 8 (08h) r4 (04h) 1 bit bit 0 01h 0h 0b bias_ena = 1 (delay = 0.5625ms) 9 (09h) r14 (0eh) 2 bits bit 0 03h 0h 0b hpl_pga_ena = 1 hpr_pga_ena = 1 (delay = 0.5625ms) 10 (0ah) r13 (dh) 2 bits bit 0 03h 0h 0b mixoutl = 1 mixoutr = 1 (delay = 0.5625ms) 11 (0bh) r15 (0fh) 2 bits bit 0 03h 0h 0b lineoutl_pga_ena = 1 lineoutr_pga_ena = 1 (delay = 0.5625ms) 12 (0ch) r22 (16h) 1 bit bit 1 01h 0h 0b clk_dsp_ena = 1 (delay = 0.5625ms) 13 (0dh) r18 (12h) 2 bits bit 2 03h 5h 0b dacl_ena = 1 dacr_ena = 1 (delay = 2.5ms) 14 (0eh) r255 (ffh) 1 bit bit 0 00h 0h 0b dummy write for expansion (delay = 0.5625ms) 15 (0fh) r4 (04h) 1 bit bit 4 00h 0h 0b pobctrl = 0 (delay = 0.5625ms) 16 (10h) r98 (62h) 1 bit bit 0 01h 6h 0b cp_ena = 1 (delay = 4.5ms) 17 (11h) r255 (ffh) 1 bit bit 0 00h 0h 0b dummy write for expansion (delay = 0.5625ms) 18 (12h) r90 (5ah) 8 bits bit 0 11h 0h 0b hpl_ena = 1 hpr_ena = 1 (delay = 0.5625ms) 19 (13h) r94 (5eh) 8 bits bit 0 11h 0h 0b lineoutl_ena = 1 lineoutr_ena = 1 (delay = 0.5625ms) 20 (14h) r90 (5ah) 8 bits bit 0 33h 0h 0b hpl_ena_dly = 1 hpr_ena_dly = 1 (delay = 0.5625ms) 21 (15h) r94 (5eh) 8 bits bit 0 33h 0h 0b lineoutl_ena_dly = 1 lineoutr_ena_dly = 1 (delay = 0.5625ms) 22 (16h) r69 (45h) 2 bits bit 0 02h 0h 0b dcs_mode = 10 (delay = 0.5625ms) 23 (17h) r67 (43h) 4 bits bit 0 0fh ch 0b dcs_ena = 1111 (delay = 256.5ms) 24 (18h) r67 (43h) 4 bits bit 0 0fh 7h 0b dcs_ena = 1111 (delay = 8.5ms) 25 (19h) r255 (ffh) 1 bit bit 0 00h 0h 0b dummy write for expansion (delay = 0.5625ms) 26 (1ah) r90 (5ah) 8 bits bit 0 77h 0h 0b hpl_ena_outp = 1 hpr_ena_outp = 1 (delay = 0.5625ms)
WM8903 production data w pd, rev 4.5, june 2012 124 wseq index register address width start data delay eos description 27 (1bh) r94 (5eh) 8 bits bit 0 77h 0h 0b lineoutl_ena_outp = 1 lineoutr_ena_outp = 1 (delay = 0.5625ms) 28 (1ch) r90 (5ah) 8 bits bit 0 ffh 0h 0b hpl_rmv_short = 1 hpr_rmv_short = 1 (delay = 0.5625ms) 29 (1dh) r94 (5eh) 8 bits bit 0 ffh 0h 1b lineoutl_rmv_short = 1 lineoutr_rmv_short = 1 end of sequence 30 (1eh) r255 (ffh) 1 bit bit 0 00h 0h 0b spare 31 (1fh) r255 (ffh) 1 bit bit 0 00h 0h 0b spare table 79 start-up sequence
production data WM8903 w pd, rev 4.5, june 2012 125 shutdown sequence the shutdown sequence is initiated by writing 0120h to register r111 (6fh). this single operation starts the control write sequencer at index a ddress 32 (20h) and executes the sequence defined in table 80. for typical clocking configurations with mclk =12.288mhz, this sequence takes approximately 325ms to run. wseq index register address width start data delay eos description 32 (20h) r94 (5eh) 8 bits bit 0 77h 0h 0b lineoutl_rmv_short = 0 lineoutr_rmv_short = 0 (delay = 0.5625ms) 33 (21h) r90 (5ah) 8 bits bit 0 77h 0h 0b hpl_rmv_short = 0 hpr_rmv_short = 0 (delay = 0.5625ms) 34 (22h) r90 (5ah) 8 bits bit 0 00h 0h 0b hpl_ena_outp = 0 hpl_ena_dly = 0 hpl_ena = 0 hpr_ena_outp = 0 hpr_ena_dly = 0 hpr_ena = 0 (delay = 0.5625ms) 35 (23h) r94 (5eh) 8 bits bit 0 00h 0h 0b lineoutl_ena_outp = 0 lineoutl_ena_dly = 0 lineoutl_ena = 0 lineoutr_ena_outp = 0 lineoutr_ena_dly = 0 lineoutr_ena = 0 (delay = 0.5625ms) 36 (24h) r67 (43h) 4 bits bit 0 00h 0h 0b dcs_ena = 0000 (delay = 0.5625ms) 37 (25h) r98 (62h) 1 bit bit 0 00h 0h 0b cp_ena = 0 (delay = 0.5625ms) 38 (26h) r18 (12h) 2 bits bit 2 00h 0h 0b dacl_ena = 0 dacr_ena = 0 (delay = 0.5625ms) 39 (27h) r22 (16h) 1 bit bit 1 00h 0h 0b clk_dsp_ena = 0 (delay = 0.5625ms) 40 (28h) r14 (0eh) 2 bits bit 0 00h 0h 0b hpl_pga_ena = 0 hpr_pga_ena = 0 (delay = 0.5625ms) 41 (29h) r15 (0fh) 2 bits bit 0 00h 0h 0b lineoutl_pga_ena = 0 lineoutr_pga_ena = 0 (delay = 0.5625ms) 42 (2ah) r13 (0dh) 2 bits bit 0 00h 0h 0b mixoutl_ena = 0 mixoutr_ena = 0 (delay = 0.5625ms) 43 (2bh) r4 (04h) 1 bit bit 0 00h 0h 0b bias_ena = 0 (delay = 0.5625ms) 44 (2ch) r5 (05h) 2 bits bit 3 02h 0h 0b vmid_soft = 10 (delay = 0.5625ms) 45 (2dh) r5 (05h) 1 bit bit 0 00h ch 0b vmid_buf_ena = 0 (delay = 256.5ms) 46 (2eh) r5 (05h) 1 bit bit 0 00h 9h 0b vmid_buf_ena = 0
WM8903 production data w pd, rev 4.5, june 2012 126 wseq index register address width start data delay eos description (delay = 32.5ms) 47 (2fh) r5 (05h) 8 bits bit 0 00h 0h 0b vmid_tie_ena = 0 bufio_ena = 0 vmid_io_ena = 0 vmid_soft = 00 vmid_res = 00 vmid_buf_ena = 0 (delay = 0.5625ms) 48 (30h) r4 (04h) 2 bits bit 0 00h 0h 1b startup_bias_ena = 0 bias_ena = 0 end of sequence table 80 shutdown sequence
production data WM8903 w pd, rev 4.5, june 2012 127 power-on reset the WM8903 includes an internal power-on-reset (por ) circuit, which is used to reset the digital logic into a default state after power up. the por circuit is powered from avdd and monitors dcvdd. the internal por signal is asserted low when avdd or dcvdd are below minimum thresholds. the specific behaviour of the circuit will vary, depending on the relative timing of the supply voltages. typical scenarios are illustrated in figure 65 and figure 66. dcvdd v pord_on 0v avdd 0v v pora v pora_off lo hi internal por device ready por active por active por undefined addr/gpio3 lo hi t pusetup t puhold figure 65 power on reset timing - avdd enabled first figure 66 power on reset timing - dcvdd enabled first
WM8903 production data w pd, rev 4.5, june 2012 128 the por signal is undefined until avdd has exceeded the minimum threshold, v pora once this threshold has been exceeded, por is asserted low and the chip is held in reset. in this condition, all writes to the control interface are ignored. once avdd and dcvdd have r eached their respective power on thresholds, por is released high, all registers are in their default state, and writes to the control interface may take place. note that a minimum power-on reset period, t por , applies even if avdd and dcvdd have zero rise time. (this specification is guarant eed by design rather than test.) on power down, por is asserted low when any of avdd or dcvdd falls below their respective power-down thresholds. typical power-on reset parameters for the WM8903 are defined in table 81. symbol description typ unit v pora avdd threshold below which por is undefined 0.5 v v pora_on power-on threshold (avdd) 1.15 v v pora_off power-off threshold (avdd) 1.12 v v pord_on power-on threshold (dcvdd) 0.57 v v pord_off power-off threshold (dcvdd) 0.56 v t por minimum power-on reset period 10.6 ? s table 81 typical power-on reset parameters notes: 1. if avdd and dcvdd suffer a brown-out (i.e. drop below the minimum recommended operating level but do not go below v pora_off or v pord_off ) then the chip does not reset and resumes normal operation when the voltage is back to the recommended level again. 2. the chip enters reset at power down when avdd or dcvdd falls below v pora_off or v pord_off . this may be important if the supply is turned on and off frequently by a power management system. 3. the minimum t por period is maintained even if dcvdd and avdd have zero rise time. this specification is guaranteed by design rather than test. 4. see ?control interface? section for details of t pusetup and t puhold .
production data WM8903 w pd, rev 4.5, june 2012 129 quick start-up and shutdown the WM8903 has the capability to perform a quick st art-up and shut-down with a minimum number of register operations. this is ac hieved using the control write s equencer, which is configured with default start-up settings that set up the devic e for dac playback via headphone and line output. assuming a 12.288mhz external clock, the star t-up sequence configures the device for 48khz playback mode. the default start-up sequence requires three regi ster write operations. the default shutdown sequence requires just a single register write. t he minimum procedure for executing the quick start- up and shutdown sequences is descr ibed below. see ?control write sequencer? for more details. quick start-up (default sequence) an external clock must be applied to mclk. assu ming 12.288mhz input clock, the start-up sequence will take approximately 425ms to complete. the following register operations will initiate the quick start-up sequence. register address value description r108 (6ch) write sequencer 0 0100h wsmd_clk_ena = 1 this enables the write sequencer clock r22 (16h) clock rates 2 0004h clk_sys_ena = 1 this enables the system clock r111 (6fh) write sequencer 3 0100h wseq_start_index = 00h wseq_start = 1 wseq_abort = 0 this starts the write sequenc er at index address 0 (00h) table 82 quick start-up control the wseq_busy bit (in register r112, see tabl e 76) will be set to 1 while the sequence runs. when this bit returns to 0, the device has been set up and is ready for dac playback operation. quick shutdown (default sequence) the default shutdown sequence assumes the initial dev ice conditions are as c onfigured by the default start-up sequence. assuming 12.288mhz input clock, the shutdown sequence will take approximately 325ms to complete. the following register operation will in itiate the default shut-down sequence. register address value description r111 (6fh) write sequencer 3 0120h wseq_start_index = 20h wseq_start = 1 wseq_abort = 0 this starts the write sequenc er at index address 32 (20h) table 83 quick shutdown control the wseq_busy bit (in register r112, see tabl e 76) will be set to 1 while the sequence runs. when this bit returns to 0, the system clo ck can be disabled (clk_sys _ena=0) and mclk can be stopped.
WM8903 production data w pd, rev 4.5, june 2012 130 software reset and chip id a software reset can be commanded by writing to regi ster r0. this is a read-only register field and the contents will not be affected by writing to this register. the chip id can be read back from register r0 . the chip revision id can be read back from register 1, as described in table 84. register address bit label default description r0 (00h) sw reset and id 15:0 sw_rst_de c_id1 [15:0] 8903h writing to this regist er resets all registers to their default state. reading from this register will indicate device id 8903h. r1 (01h) revision number 3:0 chip_rev [3:0] 0010b reading from this register will indicate the revision id. (read-only register) table 84 software reset and chip id
production data WM8903 w pd, rev 4.5, june 2012 131 register map dec addr hex addr name 1514131211109876543210 bin default 0 00 sw reset and id 1000_1001_0000_0011 101revision number 000000000000 0000_0000_0000_0000 404bias control 0 00000000000pobctrl startup_bias_ ena bias_ena 0000_0000_0001_1000 505vmid control 0 00000000 vmid_tie_ena bufio_ena vmid_io_ena vmid_buf_ena 0000_0000_0000_0000 606mic bias control 0 0000000000 micdet_ena micbias_ena 0000_0000_0000_0000 8 08 analogue dac 0 0 0 0 0000000 dac_bias_boo st 1 0000_0000_0000_0001 10 0a analogue adc 0 0 0 0 000000000000adc_osr128 0000_0000_0000_0001 12 0c power management 0 0 0 0 00000000000inl_enainr_ena 0000_0000_0000_0000 13 0d power management 1 0 0 0 00000000000mixoutl_enamixoutr_ena 0000_0000_0000_0000 14 0e power management 2 0 0 0 00000000000hpl_pga_enahpr_pga_ena 0000_0000_0000_0000 15 0f power management 3 0 0 0 00000000000 lineoutl_pga_ ena lineoutr_pga _ena 0000_0000_0000_0000 16 10 power management 4 0 0 0 00000000000mi xspkl_ena mix spkr_ena 0000_0000_0000_0000 17 11 power management 5 0 0 0 00000000000spkl_enaspkr_ena 0000_0000_0000_0000 18 12 power management 6 0 0 0 000000000dacl_enadacr_enaadcl_enaadcr_ena 0000_0000_0000_0000 2014clock rates 0 000001000000000mclkdiv2 0000_0100_0000_0000 21 15 clock rates 1 clk_src_sel 0 0000 0000_1100_0000_1000 2216clock rates 2 0000000000000clk_sys_enaclk_dsp_enato_ena 0000_0000_0000_0000 24 18 audio interface 0 0 0 0 dacl_datinv dacr_datinv loopback aifadcl_src aifadcr_src aifdacl_src aifdacr_src adc_comp adc_compmod e dac_comp dac_compmod e 0000_0000_0101_0000 25 19 audio interface 1 0 0 aifdac_tdm aifdac_tdm_chan aifadc_tdm aifadc_tdm_chan lrclk_dir 0 aif_bclk_inv bclk_dir 0 aif_lrclk_inv 0000_0000_0000_0010 261aaudio interface 2 00000000000 0000_0000_0000_1000 27 1b audio interface 3 0 0 0 0 0 0000_0000_0010_0010 301edac digital volume left0000000dacvu 0000_000p_1100_0000 311fdac digital volume right0000000dacvu 0000_000p_1100_0000 32 20 dac digital 0 0 0 0 0 0000_0000_0000_0000 33 21 dac digital 1 0 0 0 dac_mono dac_sb_filt dac_muterat e dac_mutemod e 00000dac_mute dac_osr 0000_0000_0000_0000 3624adc digital volume left0000000adcvu 0000_000p_1100_0000 3725adc digital volume right0000000adcvu 0000_000p_1100_0000 3826adc digital 0 000000000 adc_hpf_ena00adcl_datinva dcr_dati nv 0000_0000_0001_0000 micdet_thr[1:0] dacvmid_bias_sel[1:0] aif_wl[1:0] lrclk_rate[10:0] clk_sys_rate[3:0] bclk_div[4:0] aif_fmt[1:0] adcr_dac_svol[3:0] adcl_dac_svol[3:0] adcl_vol[7:0] deemph[1:0] adc_hpf_cut[1:0] sw_rst_dev_id1[15:0] chip_rev[3:0] vmid_res[1:0] isel[1:0] micshort_thr[1:0] vmid_soft[1:0] dacbias_sel[1:0] clk_sys_mode[1:0] sample_rate[3:0] adcr_vol[7:0] dacr_vol[7:0] adc_to_dacr[1:0] dacl_vol[7:0] dac_boost[1:0] adc_to_dacl[1:0]
WM8903 production data w pd, rev 4.5, june 2012 132 dec addr hex addr name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bin default 40 28 drc 0 drc_ena 0 drc_ff_delay 0 drc_smooth_ ena drc_qr_ena drc_anticlip_ ena drc_hyst_ena 0000_1001_1011_1111 41 29 drc 1 0011_0010_0100_0001 422adrc 2 0000000000 0000_0000_0010_0000 43 2b drc 3 0 0 0 0 0 0000_0000_0000_0000 44 2c analogue left input 0 0 0 0 0 0 0 0 0 linmute 0 0 0000_0000_1000_0101 45 2d analogue right input 0 0 0 0 0 0 0 0 0 rinmute 0 0 0000_0000_1000_0101 46 2e analogue left input 1 0 0 0 0 0 0 0 0 0 inl_cm_ena 0000_0000_0100_0100 47 2f analogue right input 1 0 0 0 0 0 0 0 0 0 inr_cm_ena 0000_0000_0100_0100 50 32 analogue left mix 0 0 0 0 0 0 0 0 0 0 0 0 0 dacl_to_mixo utl dacr_to_mixo utl bypassl_to_m ixoutl bypassr_to_m ixoutl 0000_0000_0000_1000 51 33 analogue right mix 0 0 0 0 0 0 0 0 0 0 0 0 0 dacl_to_mixo utr dacr_to_mixo utr bypassl_to_m ixoutr bypassr_to_m ixoutr 0000_0000_0000_0100 52 34 analogue spk mix left 0 0 0 0 0 0 0 0 0 0 0 0 0 dacl_to_mixs pkl dacr_to_mixs pkl bypassl_to_m ixspkl bypassr_to_m ixspkl 0000_0000_0000_0000 53 35 analogue spk mix left 1 0 0 0 0 0 0 0 0 0 0 0 0 dacl_mixspkl_ vol dacr_mixspkl _vol bypassl_mixs pkl_vol bypassr_mixs pkl_vol 0000_0000_0000_0000 54 36 analogue spk mix right 0 0 0 0 0 0 0 0 0 0 0 0 0 dacl_to_mixs pkr dacr_to_mixs pkr bypassl_to_m ixspkr bypassr_to_m ixspkr 0000_0000_0000_0000 55 37 analogue spk mix right 1 0 0 0 0 0 0 0 0 0 0 0 0 dacl_mixspkr _vol dacr_mixspkr _vol bypassl_mixs pkr_vol bypassr_mixs pkr_vol 0000_0000_0000_0000 57 39 analogue out1 left 0 0 0 0 0 0 0 hpl_mute hpoutvu hpoutlzc 0000_0000_p010_1101 58 3a analogue out1 right 0 0 0 0 0 0 0 hpr_mute hpoutvu hpoutrzc 0000_0000_p010_1101 59 3b analogue out2 left 0 0 0 0 0 0 0 lineoutl_mute lineoutvu lineoutlzc 0000_0000_p011_1001 60 3c analogue out2 right 0 0 0 0 0 0 0 lineoutr_mute lineoutvu lineoutrzc 0000_0000_p011_1001 62 3e analogue out3 left 0 0 0 0 0 0 0 spkl_mute spkvu spklzc 0000_0001_p011_1001 63 3f analogue out3 right 0 0 0 0 0 0 0 spkr_mute spkvu spkrzc 0000_0001_p011_1001 65 41 analogue spk output control 0 00000000000000 spk_discharge vroi 0000_0000_0000_0000 6743dc servo 0 00000000000 dcs_master_e na 0000_0000_0001_0000 69 45 dc servo 2 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0000_0000_1010_0100 71 47 dc servo 4 0 0 0 0 0 0 0 0 0000_0000_0000_0000 72 48 dc servo 5 0 0 0 0 0 0 0 0 0000_0000_0000_0000 73 49 dc servo 6 0 0 0 0 0 0 0 0 0000_0000_0000_0000 74 4a dc servo 7 0 0 0 0 0 0 0 0 0000_0000_0000_0000 81 51 dc servo readback 1 0 0 0 0 0 0 0 0 0000_0000_0000_0000 82 52 dc servo readback 2 0 0 0 0 0 0 0 0 0000_0000_0000_0000 83 53 dc servo readback 3 0 0 0 0 0 0 0 0 0000_0000_0000_0000 84 54 dc servo readback 4 0 0 0 0 0 0 0 0 0000_0000_0000_0000 dcs_loutl_write_val[7:0] dcs_hpoutl_write_val[7:0] l_ip_sel_p[1:0] drc_r1_slope_comp[2:0] lin_vol[4:0] dcs_loutr_write_val[7:0] drc_r0_slope_comp[2:0] l_mode[1:0] dcs_hpoutl_integ[7:0] l_ip_sel_n[1:0] drc_amp_comp[4:0] hpoutl_vol[5:0] dcs_hpoutr_integ[7:0] dcs_hpoutr_write_val[7:0] rin_vol[4:0] drc_maxgain[1:0] drc_mingain[1:0] drc_rate_qr[1:0] drc_startup_gain[4:0] drc_thresh_hyst[1:0] drc_thresh_qr[1:0] r_ip_sel_p[1:0] r_ip_sel_n[1:0] r_mode[1:0] lineoutl_vol[5:0] lineoutr_vol[5:0] spkl_vol[5:0] spkr_vol[5:0] drc_attack_rate[3:0] drc_decay_rate[3:0] drc_thresh_comp[5:0] dcs_loutr_integ[7:0] dcs_loutl_integ[7:0] dcs_ena[3:0] hpoutr_vol[5:0] dcs_mode[1:0]
production data WM8903 w pd, rev 4.5, june 2012 133 dec addr hex addr name 1514131211109876543210 bin default 90 5a analogue hp 0 0 0 0 00000 hpl_rmv_sho rt hpl_ena_outp hpl_ena_dly hpl_ena hpr_rmv_sho rt hpr_ena_outp hpr_ena_dly hpr_ena 0000_0000_0000_0000 94 5e analogue lineout 0 0 0 0 00000 lineoutl_rmv _short lineoutl_ena_ outp lineoutl_ena_ dly lineoutl_ena lineoutr_rmv _short lineoutr_ena _outp lineoutr_ena _dly lineoutr_ena 0000_0000_0000_0000 9862charge pump 0 000000000000000cp_ena 0000_0000_0000_0000 104 68 class w 0 0000000000 01 0 0 0 cp_dyn_pwr 0000_0000_0001_0000 108 6c write sequencer 0 0 0 0 0000 wsmd_clk_en a 000 0000_0000_0000_0000 109 6d write sequencer 1 0 0000_0000_0000_0000 110 6e write sequencer 2 0 wseq_eos 0 0 0000_0000_0000_0000 111 6f write sequencer 3 0 0 0 0 0 0 wseq_abort wseq_start 0 0 0000_0000_0000_0000 112 70 write sequencer 4 0 0 0 0 0 0 0 0 0 wseq_busy 0000_0000_0000_0000 116 74 gpio control 1 0 0 gp1_dir gp1_op_cfg gp1_ip_cfg gp1_lvl gp1_pd gp1_pu gp1_intmode gp1_db 0000_0000_1010_1000 117 75 gpio control 2 0 0 gp2_dir gp2_op_cfg gp2_ip_cfg gp2_lvl gp2_pd gp2_pu gp2_intmode gp2_db 0000_0000_1010_1000 118 76 gpio control 3 0 0 gp3_dir gp3_op_cfg gp3_ip_cfg gp3_lvl gp3_pd gp3_pu gp3_intmode gp3_db 0000_0000_1010_1000 119 77 gpio control 4 0 0 gp4_dir gp4_op_cfg gp4_ip_cfg gp4_lvl gp4_pd gp4_pu gp4_intmode gp4_db 0000_0010_0010_0000 120 78 gpio control 5 0 0 gp5_dir gp5_op_cfg gp5_ip_cfg gp5_lvl gp5_pd gp5_pu gp5_intmode gp5_db 0000_0001_1010_0000 121 79 interrupt status 1 micshrt_eint micdet_eint wseq_busy_ei nt 0000000f ll_lock_eint gp5_eint gp4_eint gp3_eint gp2_eint gp1_eint 0000_0000_0000_0000 122 7a interrupt status 1 mask im_micshrt_ei nt im_micdet_ein t im_wseq_busy _eint 1111111 im_fll_lock_e int im_gp5_eint im_gp4_eint im_gp3_eint im_gp2_eint im_gp1_eint 1111_1111_1111_1111 1237binterrupt polarity 1micshrt_invmicdet_inv00000000f ll_lock_inv 0 0 0 0 0 0000_0000_0000_0000 1267einterrupt control 000000000000000irq_pol 0000_0000_0000_0000 12880fll control 1 00000000 fll_hold fll_frac 0 fll_ena 0000_0000_0000_0000 129 81 fll control 2 000 0000_0000_0000_0000 130 82 fll control 3 0000_0000_0000_0000 131 83 fll control 4 000000 0000_0000_0000_0000 164a4clock rate test 4 001010adc_dig_mic000111000 0010_1000_0011_1000 172 ac analogue output bias 0 0 0 0 000000 0 0 0 0 0000_0000_0000_0000 187 bb analogue output bias 2 0 0 0 0000000000 0000_0000_0000_0000 pga_bias[2:0] gp4_fn[5:0] wseq_data_start[3:0] wseq_addr[7:0] wseq_start_index[5:0] wseq_current_index[5:0] gp1_fn[5:0] gp2_fn[5:0] wseq_data_width[2:0] fll_clk_ref_div[1:0] fll_gain[3:0] wseq_delay[3:0] fll_clk_src[1:0] wseq_write_index[4:0] fll_fratio[2:0] fll_ctrl_rate[2:0] fll_outdiv[2:0] wseq_data[7:0] gp3_fn[5:0] fll_k[15:0] fll_n[9:0] outputs_bias[2:0] gp5_fn[5:0]
WM8903 production data w pd, rev 4.5, june 2012 134 register bits by address register address bit label default description r0 (00h) sw reset and id 15:0 sw_rst_dev_id1 [15:0] 1000_1001_0000_0011 writing to this register resets all registers to their default state. reading from this register will indicate device id 8903h. register 00h sw reset and id register address bit label default description r1 (01h) revision number 3:0 chip_rev [3:0] 0010 reading from this register will indicate the revision id. (read-only register) register 01h revision number register address bit label default description r4 (04h) bias control 0 4 pobctrl 1 selects the bias current source for output amplifiers and vmid buffer 0 = default bias 1 = start-up bias 3:2 isel [1:0] 10 master bias control 00 = normal bias x 0.5 01 = normal bias x 0.75 10 = normal bias 11 = normal bias x 1.5 1 startup_bias_ena 0 enables the start-up bias current generator 0 = disabled 1 = enabled 0 bias_ena 0 enables the normal bias current generator (for all analogue functions) 0 = disabled 1 = enabled register 04h bias control 0 register address bit label default description r5 (05h) vmid control 0 7 vmid_tie_ena 0 vmid buffer to differential lineouts 0 = disabled 1 = enabled (only applies when relevant outputs are disabled, ie. splk=0 or spkr=0. resistance is controlled by vroi.) 6 bufio_ena 0 vmid buffer to unused input and output pins. 0 = disabled 1 = enabled 5 vmid_io_ena 0 enables the start-up bias current generator 0 = disabled 1 = enabled (same functionality as startup_bias_ena)
production data WM8903 w pd, rev 4.5, june 2012 135 register address bit label default description 4:3 vmid_soft [1:0] 00 vmid soft start enable / slew rate control 00 = disabled 01 = fast soft start 10 = nominal soft start 11 = slow soft start 2:1 vmid_res [1:0] 00 vmid divider enable and select 00 = vmid disabled (for off mode) 01 = 2 x 50k divider (for normal operation) 10 = 2 x 250k divider (for low power standby) 11 = 2 x 5k divider (for fast start-up) 0 vmid_buf_ena 0 vmid buffer enable 0 = disabled 1 = enabled register 05h vmid control 0 register address bit label default description r6 (06h) mic bias control 0 5:4 micdet_thr [1:0] 00 micbias current detect insertion threshold 00 = 0.063ma 01 = 0.26ma 10 = 0.45ma 11 = 0.635ma values are scaled with avdd. figures shown are based on avdd=1.8v. 3:2 micshort_thr [1:0] 00 micbias short circuit button push threshold 00 = 0.52ma 01 = 0.77ma 10 = 1.2ma 11 = 1.43ma values are scaled with avdd. figures shown are based on avdd=1.8v. 1 micdet_ena 0 micbias current and short circuit detect enable 0 = disabled 1 = enabled 0 micbias_ena 0 micbias enable 0 = disabled 1 = enabled register 06h mic bias control 0 register address bit label default description r8 (08h) analogue dac 0 5 dac_bias_boost 0 dac bias boost 0 = disable 1 = enable when dac bias boost is enabled, the bias selected by dacbias_sel and dacvmid_bias_sel are both doubled. 4:3 dacbias_sel [1:0] 00 dac bias current select 00 = normal bias 01 = normal bias x 0.5 10 = normal bias x 0.66
WM8903 production data w pd, rev 4.5, june 2012 136 register address bit label default description 11 = normal bias x 0.75 2:1 dacvmid_bias_sel [1:0] 00 dac vmid buffer bias select 00 = normal bias 01 = normal bias x 0.5 10 = normal bias x 0.66 11 = normal bias x 0.75 register 08h analogue dac 0 register address bit label default description r10 (0ah) analogue adc 0 0 adc_osr128 1 adc oversampling ratio 0 = low power (64 x fs) 1 = high performance (128 x fs) note that the low power options is not supported when clk_sys_mode=10 register 10h analogue adc 0 register address bit label default description r12 (0ch) power management 0 1 inl_ena 0 left input pga enable 0 = disabled 1 = enabled 0 inr_ena 0 right input pga enable 0 = disabled 1 = enabled register 0ch power management 0 register address bit label default description r13 (0dh) power management 1 1 mixoutl_ena 0 left output mixer enable 0 = disabled 1 = enabled 0 mixoutr_ena 0 right output mixer enable 0 = disabled 1 = enabled register 0dh power management 1 register address bit label default description r14 (0eh) power management 2 1 hpl_pga_ena 0 left headphone output enable 0 = disabled 1 = enabled 0 hpr_pga_ena 0 right headphone output enable 0 = disabled 1 = enabled register 0eh power management 2
production data WM8903 w pd, rev 4.5, june 2012 137 register address bit label default description r15 (0fh) power management 3 1 lineoutl_pga_ena 0 left line output enable 0 = disabled 1 = enabled 0 lineoutr_pga_ena 0 right line output enable 0 = disabled 1 = enabled register 0fh power management 3 register address bit label default description r16 (10h) power management 4 1 mixspkl_ena 0 left speaker mixer enable 0 = disabled 1 = enabled 0 mixspkr_ena 0 right speaker mixer enable 0 = disabled 1 = enabled register 10h power management 4 register address bit label default description r17 (11h) power management 5 1 spkl_ena 0 left speaker output enable 0 = disabled 1 = enabled 0 spkr_ena 0 right speaker output enable 0 = disabled 1 = enabled register 11h power management 5 register address bit label default description r18 (12h) power management 6 3 dacl_ena 0 left dac enable 0 = dac disabled 1 = dac enabled 2 dacr_ena 0 right dac enable 0 = dac disabled 1 = dac enabled 1 adcl_ena 0 left adc enable 0 = disabled 1 = enabled 0 adcr_ena 0 right adc enable 0 = disabled 1 = enabled register 12h power management 6
WM8903 production data w pd, rev 4.5, june 2012 138 register address bit label default description r20 (14h) clock rates 0 0 mclkdiv2 0 enables divide by 2 on mclk 0 = clk_sys = mclk 1 = clk_sys = mclk / 2 register 14h clock rates 0 register address bit label default description r21 (15h) clock rates 1 15 clk_src_sel 0 sysclk source select 0 = mclk 1 = fll output 13:10 clk_sys_rate [3:0] 0011 clk_sys / sample rate (fs) ratio if clk_sys_mode = 00 (256*fs related clocks) 0000 = 64*fs 0001 = 128*fs 0010 = 192*fs 0011 = 256*fs 0100 = 384*fs 0101 = 512*fs 0110 = 768*fs 0111 = 1024 *fs 1000 = 1408*fs 1001 = 1536*fs 1010 to 1111 = reserved if clk_sys_mode = 01 (272*fs related clocks) 0000 = 68*fs 0001 = 136*fs 0010 = 204*fs 0011 = 272*fs 0100 = 408*fs 0101 = 544*fs 0110 = 816*fs 0111 = 1088 *fs 1000 = 1496*fs 1001 = 1632*fs 1010 to 1111 = reserved if clk_sys_mode = 10 (250*fs related clocks) 0000 = 125*fs 0001 = 125*fs 0010 = 250*fs 0011 = 250*fs 0100 = 375*fs 0101 = 500*fs 0110 = 750*fs 0111 = 1000 *fs 1000 = 1000*fs 1001 = 1500*fs 1010 to 1111 = reserved
production data WM8903 w pd, rev 4.5, june 2012 139 register address bit label default description 9:8 clk_sys_mode [1:0] 00 clk_sys mode 00 = 256*fs related 01 = 272*fs related 10 = 250*fs related 11 = reserved 3:0 sample_rate [3:0] 1000 selects the sample rate (fs) 0000 = 8khz 0001 = 11.025khz 0010 = 12khz 0011 = 16khz 0100 = 22.05khz 0101 = 24khz 0110 = 32khz 0111 = 44.1khz 1000 = 48khz 1001 = 88.2khz (not available for digital microphone. not used for 88.2khz adc.) 1010 = 96khz (not available for digital microphone. not used for 96khz adc). 1011 to 1111 = reserved if the desired sample rate is not listed in this table, then the closes t alternative should be chosen. register 15h clock rates 1 register address bit label default description r22 (16h) clock rates 2 2 clk_sys_ena 0 system clock enable 0 = disabled 1 = enabled 1 clk_dsp_ena 0 dsp clock enable 0 = disabled 1 = enabled 0 to_ena 0 zero cross timeout enable 0 = disabled 1 = enabled register 16h clock rates 2 register address bit label default description r24 (18h) audio interface 0 12 dacl_datinv 0 left dac invert 0 = left dac output not inverted 1 = left dac output inverted 11 dacr_datinv 0 right dac invert 0 = right dac output not inverted 1 = right dac output inverted
WM8903 production data w pd, rev 4.5, june 2012 140 register address bit label default description 10:9 dac_boost [1:0] 00 dac digital input volume boost 00 = 0db 01 = +6db (input data must not exceed -6dbfs) 10 = +12db (input data must not exceed -12dbfs) 11 = +18db (input data must not exceed -18dbfs) 8 loopback 0 digital loopback function 0 = no loopback 1 = loopback enabled (adc data output is directly input to dac data input) 7 aifadcl_src 0 left digital audio channel source 0 = left adc data is output on left channel 1 = right adc data is output on left channel 6 aifadcr_src 1 right digital audio channel source 0 = left adc data is output on right channel 1 = right adc data is output on right channel 5 aifdacl_src 0 left dac data source select 0 = left dac outputs left channel data 1 = left dac outputs right channel data 4 aifdacr_src 1 right dac data source select 0 = right dac outputs left channel data 1 = right dac outputs right channel data 3 adc_comp 0 adc companding enable 0 = disabled 1 = enabled 2 adc_compmode 0 adc companding type 0 = -law 1 = a-law 1 dac_comp 0 dac companding enable 0 = disabled 1 = enabled 0 dac_compmode 0 dac companding type 0 = -law 1 = a-law register 18h audio interface 0 register address bit label default description r25 (19h) audio interface 1 13 aifdac_tdm 0 dac tdm enable 0 = normal dacdat operation 1 = tdm enabled on dacdat 12 aifdac_tdm_chan 0 dacdat tdm channel select 0 = dacdat data input on slot 0 1 = dacdat data input on slot 1 11 aifadc_tdm 0 adc tdm enable 0 = normal adcdat operation 1 = tdm enabled on adcdat 10 aifadc_tdm_chan 0 adcdat tdm channel select 0 = adcdat outputs data on slot 0 1 = adcdat output data on slot 1
production data WM8903 w pd, rev 4.5, june 2012 141 register address bit label default description 9 lrclk_dir 0 audio interface lrc direction 0 = lrc is input 1 = lrc is output 7 aif_bclk_inv 0 bclk invert 0 = bclk not inverted 1 = bclk inverted 6 bclk_dir 0 audio interface bclk direction 0 = bclk is input 1 = bclk is output 4 aif_lrclk_inv 0 lrc polarity / dsp mode a-b select. right, left and i2s modes ? lrc polarity 0 = not inverted 1 = inverted dsp mode ? mode a-b select 0 = msb is available on 2nd bclk rising edge after lrc rising edge (mode a) 1 = msb is available on 1st bclk rising edge after lrc rising edge (mode b) 3:2 aif_wl [1:0] 00 digital audio interface word length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits 1:0 aif_fmt [1:0] 10 digital audio interface format 00 = right justified 01 = left justified 10 = i2s 11 = dsp register 19h audio interface 1 register address bit label default description r26 (1ah) audio interface 2 4:0 bclk_div [4:0] 0_1000 bclk frequency (master mode) 00000 = clk_sys 00001 = reserved 00010 = clk_sys / 2 00011 = clk_sys / 3 00100 = clk_sys / 4 00101 = clk_sys / 5 00110 = reserved 00111 = clk_sys / 6 01000 = clk_sys / 8 (default) 01001 = clk_sys / 10 01010 = reserved 01011 = clk_sys / 12 01100 = clk_sys / 16 01101 = clk_sys / 20 01110 = clk_sys / 22 01111 = clk_sys / 24
WM8903 production data w pd, rev 4.5, june 2012 142 register address bit label default description 10000 = reserved 10001 = clk_sys / 30 10010 = clk_sys / 32 10011 = clk_sys / 44 10100 = clk_sys / 48 register 1ah audio interface 2 register address bit label default description r27 (1bh) audio interface 3 10:0 lrclk_rate [10:0] 000_0010_0010 lrc rate (master mode) lrc clock output = bclk / lrclk_rate integer (lsb = 1) valid range: 8 to 2047 50:50 lrclk duty cycle is only guaranteed with even values (8, 10, ? 2046). register 1bh audio interface 3 register address bit label default description r30 (1eh) dac digital volume left 8 dacvu 0 dac volume update writing a 1 to this bit causes left and right dac volume to be updated simultaneously (write-only register) 7:0 dacl_vol [7:0] 1100_0000 left dac digital volume 00h = mute 01h = -71.625db 02h = -71.250db ? (0.375db steps) c0h to ffh = 0db register 1eh dac digital volume left register address bit label default description r31 (1fh) dac digital volume right 8 dacvu 0 dac volume update writing a 1 to this bit causes left and right dac volume to be updated simultaneously (write-only register) 7:0 dacr_vol [7:0] 1100_0000 right dac digital volume 00h = mute 01h = -71.625db 02h = -71.250db ? (0.375db steps) c0h to ffh = 0db register 1fh dac digital volume right
production data WM8903 w pd, rev 4.5, june 2012 143 register address bit label default description r32 (20h) dac digital 0 11:8 adcl_dac_svol [3:0] 0000 left digital sidetone volume 0000 = -36db 0001 = -33db (? 3db steps) 1011 = -3db 11xx = 0db 7:4 adcr_dac_svol [3:0] 0000 right digital sidetone volume 0000 = -36db 0001 = -33db (? 3db steps) 1011 = -3db 11xx = 0db 3:2 adc_to_dacl [1:0] 00 left dac digital sidetone source 00 = no sidetone 01 = left adc 10 = right adc 11 = reserved 1:0 adc_to_dacr [1:0] 00 right dac digital sidetone source 00 = no sidetone 01 = left adc 10 = right adc 11 = reserved register 20h dac digital 0 register address bit label default description r33 (21h) dac digital 1 12 dac_mono 0 dac mono mix 0 = stereo 1 = mono (mono mix output on enabled dac) 11 dac_sb_filt 0 selects dac filter characteristics 0 = normal mode 1 = sloping stopband mode (recommended when fs ??? 24khz ? 10 dac_muterate 0 dac soft mute ramp rate 0 = fast ramp (fs/2, maximum ramp time is 10.7ms at fs=48k) 1 = slow ramp (fs/32, maximum ramp time is 171ms at fs=48k) 9 dac_mutemode 0 dac soft mute mode 0 = disabling soft-mute (dac_mute=0) will cause the dac volume to change immediately to dacl_vol and dacr_vol settings 1 = disabling soft-mute (dac_mute=0) will cause the dac volume to ramp up gradually to the dacl_vol and dacr_vol settings 3 dac_mute 0 dac soft mute control 0 = dac un-mute 1 = dac mute 2:1 deemph [1:0] 00 dac de-emphasis control 00 = no de-emphasis 01 = 32khz sample rate 10 = 44.1khz sample rate
WM8903 production data w pd, rev 4.5, june 2012 144 register address bit label default description 11 = 48khz sample rate 0 dac_osr 0 dac oversampling control 0 = low power (normal oversample) 1 = high performance (double rate) register 21h dac digital 1 register address bit label default description r36 (24h) adc digital volume left 8 adcvu 0 adc volume update writing a 1 to this bit causes left and right adc volume to be updated simultaneously (write-only register) 7:0 adcl_vol [7:0] 1100_0000 left adc digital volume 00h = mute 01h = -71.625db 02h = -71.250db ? (0.375db steps) c0h = 0db ? (0.375db steps) efh = +17.625db f0h to ffh = +17.625db register 24h adc digital volume left register address bit label default description r37 (25h) adc digital volume right 8 adcvu 0 adc volume update writing a 1 to this bit causes left and right adc volume to be updated simultaneously (write-only register) 7:0 adcr_vol [7:0] 1100_0000 right adc digital volume 00h = mute 01h = -71.625db 02h = -71.250db ? (0.375db steps) c0h = 0db ? (0.375db steps) efh = +17.625db f0h to ffh = +17.625db register 25h adc digital volume right register address bit label default description r38 (26h) adc digital 0 6:5 adc_hpf_cut [1:0] 00 adc digital high pass filter cut-off frequency (fc) 00 = hi-fi mode (fc=4hz at fs=48khz) 01 = voice mode 1 (fc=127hz at fs=16khz) 10 = voice mode 2 (fc=130hz at fs=8khz) 11 = voice mode 3 (fc=267hz at fs=8khz) (note: fc scales with sample rate fs.)
production data WM8903 w pd, rev 4.5, june 2012 145 register address bit label default description 4 adc_hpf_ena 0 adc digital high pass filter enable 0 = disabled 1 = enabled 1 adcl_datinv 0 left adc invert 0 = left adc output not inverted 1 = left adc output inverted 0 adcr_datinv 0 right adc invert 0 = right adc output not inverted 1 = right adc output inverted register 26h adc digital 0 register address bit label default description r40 (28h) drc 0 15 drc_ena 0 drc enable 1 = enabled 0 = disabled 12:11 drc_thresh_hyst [1:0] 01 gain smoothing hysteresis threshold 00 = low 01 = medium (recommended) 10 = high 11 = reserved 10:6 drc_startup_gain [4:0] 0_0110 initial gain at drc startup 00000 = -18db 00001 = -15db 00010 = -12db 00011 = -9db 00100 = -6db 00101 = -3db 00110 = 0db (default) 00111 = 3db 01000 = 6db 01001 = 9db 01010 = 12db 01011 = 15db 01100 = 18db 01101 = 21db 01110 = 24db 01111 = 27db 10000 = 30db 10001 = 33db 10010 = 36db 10011 to 11111 = reserved 5 drc_ff_delay 1 feed-forward delay for anti-clip feature 0 = 5 samples 1 = 9 samples time delay can be calculat ed as 5/fs or 9/ fs, where fs is the sample rate. 3 drc_smooth_ena 1 gain smoothing enable 0 = disabled 1 = enabled
WM8903 production data w pd, rev 4.5, june 2012 146 register address bit label default description 2 drc_qr_ena 1 quick release enable 0 = disabled 1 = enabled 1 drc_anticlip_ena 1 anti-clip enable 0 = disabled 1 = enabled 0 drc_hyst_ena 1 gain smoothing hysteresis enable 0 = disabled 1 = enabled register 28h drc 0 register address bit label default description r41 (29h) drc 1 15:12 drc_attack_rate [3:0] 0011 gain attack rate (seconds/6db) 0000 = reserved 0001 = 182s 0010 = 363s 0011 = 726s (default) 0100 = 1.45ms 0101 = 2.9ms 0110 = 5.8ms 0111 = 11.6ms 1000 = 23.2ms 1001 = 46.4ms 1010 = 92.8ms 1011-1111 = reserved 11:8 drc_decay_rate [3:0] 0010 gain decay rate (seconds/6db) 0000 = 186ms 0001 = 372ms 0010 = 743ms (default) 0011 = 1.49s 0100 = 2.97s 0101 = 5.94s 0110 = 11.89s 0111 = 23.78s 1000 = 47.56s 1001-1111 = reserved 7:6 drc_thresh_qr [1:0] 01 quick release crest factor threshold 00 = 12db 01 = 18db (default) 10 = 24db 11 = 30db 5:4 drc_rate_qr [1:0] 00 quick release decay rate (seconds/6db) 00 = 0.725ms (default) 01 = 1.45ms 10 = 5.8ms 11 = reserved
production data WM8903 w pd, rev 4.5, june 2012 147 register address bit label default description 3:2 drc_mingain [1:0] 00 minimum gain the drc can use to attenuate audio signals 00 = 0db (default) 01 = -6db 10 = -12db 11 = -18db 1:0 drc_maxgain [1:0] 01 maximum gain the drc can use to boost audio signals 00 = 12db 01 = 18db (default) 10 = 24db 11 = 36db register 29h drc 1 register address bit label default description r42 (2ah) drc 2 5:3 drc_r0_slope_comp [2:0] 100 compressor slope r0 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 1/16 101 = 0 110 = reserved 111 = reserved 2:0 drc_r1_slope_comp [2:0] 000 compressor slope r1 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 0 101 = reserved 11x = reserved register 2ah drc 2 register address bit label default description r43 (2bh) drc 3 10:5 drc_thresh_comp [5:0] 00_0000 compressor threshold t (db) 000000 = 0db 000001 = -0.75db 000010 = -1.5db ? (-0.75db steps) 111100 = -45db 111101 = reserved 11111x = reserved 4:0 drc_amp_comp [4:0] 0_0000 compressor amplitude at threshold yt (db) 00000 = 0db 00001 = -0.75db 00010 = -1.5db ? (-0.75db steps)
WM8903 production data w pd, rev 4.5, june 2012 148 register address bit label default description 11110 = -22.5db 11111 = reserved register 2bh drc 3 register address bit label default description r44 (2ch) analogue left input 0 7 linmute 1 left input pga mute 0 = not muted 1 = muted 4:0 lin_vol [4:0] 0_0101 left input pga volume if l_mode = 00 (single ended) or l_mode = 01 (differential line) 00000 -1.55 00001 -1.3 00010 -1.0 00011 -0.7 00100 -0.3 00101 +0.0 (default) 00110 +0.3 00111 +0.7 01000 +1.0 01001 +1.4 01010 +1.8 01011 +2.3 01100 +2.7 01101 +3.2 01110 +3.7 01111 +4.2 10000 +4.8 10001 +5.4 10010 +6.0 10011 +6.7 10100 +7.5 10101 +8.3 10110 +9.2 10111 +10.2 11000 +11.4 11001 +12.7 11010 +14.3 11011 +16.2 11100 +19.2 11101 +22.3 11110 +25.2 11111 +28.3 if l_mode = 1x (differential mic) 00000 not valid 00001 +12 00010 +15 00011 +18
production data WM8903 w pd, rev 4.5, june 2012 149 register address bit label default description 00100 +21 00101 (default) +24 00110 +27 00111 +30 01xxx +30 1xxxx +30 register 2ch analogue left input 0 register address bit label default description r45 (2dh) analogue right input 0 7 rinmute 1 right input pga mute 0 = not muted 1 = muted 4:0 rin_vol [4:0] 0_0101 right input pga volume if r_mode = 00 (single ended) or r_mode = 01 (differential line) 00000 -1.55 00001 -1.3 00010 -1.0 00011 -0.7 00100 -0.3 00101 +0.0 (default) 00110 +0.3 00111 +0.7 01000 +1.0 01001 +1.4 01010 +1.8 01011 +2.3 01100 +2.7 01101 +3.2 01110 +3.7 01111 +4.2 10000 +4.8 10001 +5.4 10010 +6.0 10011 +6.7 10100 +7.5 10101 +8.3 10110 +9.2 10111 +10.2 11000 +11.4 11001 +12.7 11010 +14.3 11011 +16.2 11100 +19.2 11101 +22.3 11110 +25.2 11111 +28.3
WM8903 production data w pd, rev 4.5, june 2012 150 register address bit label default description if r_mode = 1x (differential mic) 00000 not valid 00001 +12 00010 +15 00011 +18 00100 +21 00101 (default) +24 00110 +27 00111 +30 01xxx +30 1xxxx +30 register 2dh analogue right input 0 register address bit label default description r46 (2eh) analogue left input 1 6 inl_cm_ena 1 left input pga common mode rejection enable 0 = disabled 1 = enabled (only available for l_mode=01 ? differential line) 5:4 l_ip_sel_n [1:0] 00 in single-ended or different ial line modes, this field selects the input pin for the inverting side of the left input path. in differential mic mode, this field selects the input pin for the non-inverting side of the left input path. 00 = in1l 01 = in2l 1x = in3l 3:2 l_ip_sel_p [1:0] 01 in single-ended or different ial line modes, this field selects the input pin for the non-inverting side of the left input path. in differential mic mode, this field selects the input pin for the inverting side of the left input path. 00 = in1l 01 = in2l 1x = in3l 1:0 l_mode [1:0] 00 sets the mode for the left analogue input: 00 = single-ended 01 = differential line 10 = differential mic 11 = reserved register 2eh analogue left input 1 register address bit label default description r47 (2fh) analogue right input 1 6 inr_cm_ena 1 right input pga common mode rejection enable 0 = disabled 1 = enabled (only available for r_mode =01 ? differential line) 5:4 r_ip_sel_n [1:0] 00 in single-ended or different ial line modes, this field selects the input pin for the inverting side of the right input path. in differential mic mode, this field selects the input pin for the non-inverting side of the right input path.
production data WM8903 w pd, rev 4.5, june 2012 151 register address bit label default description 00 = in1r 01 = in2r 1x = in3r 3:2 r_ip_sel_p [1:0] 01 in single-ended or different ial line modes, this field selects the input pin for the non-inverting side of the right input path. in differential mic mode, this field selects the input pin for the inverting side of the right input path. 00 = in1r 01 = in2r 1x = in3r 1:0 r_mode [1:0] 00 sets the mode for the right analogue input: 00 = single-ended 01 = differential line 10 = differential mic 11 = reserved register 2fh analogue right input 1 register address bit label default description r50 (32h) analogue left mix 0 3 dacl_to_mixoutl 1 left dac to left output mixer enable 0 = disabled 1 = enabled 2 dacr_to_mixoutl 0 right dac to left output mixer enable 0 = disabled 1 = enabled 1 bypassl_to_mixoutl 0 left analogue input to left output mixer enable 0 = disabled 1 = enabled 0 bypassr_to_mixoutl 0 right analogue input to left output mixer enable 0 = disabled 1 = enabled register 32h analogue left mix 0 register address bit label default description r51 (33h) analogue right mix 0 3 dacl_to_mixoutr 0 left dac to right output mixer enable 0 = disabled 1 = enabled 2 dacr_to_mixoutr 1 right dac to right output mixer enable 0 = disabled 1 = enabled 1 bypassl_to_mixoutr 0 left analogue input to right output mixer enable 0 = disabled 1 = enabled
WM8903 production data w pd, rev 4.5, june 2012 152 register address bit label default description 0 bypassr_to_mixoutr 0 right analogue input to right output mixer enable 0 = disabled 1 = enabled register 33h analogue right mix 0 register address bit label default description r52 (34h) analogue spk mix left 0 3 dacl_to_mixspkl 0 left dac to left spkr mixer enable 0 = disabled 1 = enabled 2 dacr_to_mixspkl 0 right dac to left spkr mixer enable 0 = disabled 1 = enabled 1 bypassl_to_mixspkl 0 left analogue input to left spkr mixer enable 0 = disabled 1 = enabled 0 bypassr_to_mixspkl 0 right analogue input to left spkr mixer enable 0 = disabled 1 = enabled register 34h analogue spk mix left 0 register address bit label default description r53 (35h) analogue spk mix left 1 3 dacl_mixspkl_vol 0 left dac to left spkr mixer volume control 0 = 0db 1 = -6db 2 dacr_mixspkl_vol 0 right dac to left spkr mixer volume control 0 = 0db 1 = -6db 1 bypassl_mixspkl_vol 0 left analogue input to left spkr mixer volume control 0 = 0db 1 = -6db 0 bypassr_mixspkl_vol 0 right analogue input to left spkr mixer volume control 0 = 0db 1 = -6db register 35h analogue spk mix left 1 register address bit label default description r54 (36h) analogue spk mix right 0 3 dacl_to_mixspkr 0 left dac to right spkr mixer enable 0 = disabled 1 = enabled 2 dacr_to_mixspkr 0 right dac to right spkr mixer enable 0 = disabled 1 = enabled
production data WM8903 w pd, rev 4.5, june 2012 153 register address bit label default description 1 bypassl_to_mixspkr 0 left analogue input to right spkr mixer enable 0 = disabled 1 = enabled 0 bypassr_to_mixspkr 0 right analogue input to right spkr mixer enable 0 = disabled 1 = enabled register 36h analogue spk mix right 0 register address bit label default description r55 (37h) analogue spk mix right 1 3 dacl_mixspkr_vol 0 left dac to right spkr mixer volume control 0 = 0db 1 = -6db 2 dacr_mixspkr_vol 0 right dac to right spkr mixer volume control 0 = 0db 1 = -6db 1 bypassl_mixspkr_vol 0 left analogue input to right spkr mixer volume control 0 = 0db 1 = -6db 0 bypassr_mixspkr_vol 0 right analogue input to right spkr mixer volume control 0 = 0db 1 = -6db register 37h analogue spk mix right 1 register address bit label default description r57 (39h) analogue out1 left 8 hpl_mute 0 left headphone output mute 0 = un-mute 1 = mute 7 hpoutvu 0 headphone output volume update writing a 1 to this bit will update hpoutl and hpoutr volumes simultaneously. (write-only register) 6 hpoutlzc 0 left headphone output zero cross enable 0 = disabled 1 = enabled 5:0 hpoutl_vol [5:0] 10_1101 left headphone output volume 000000 = -57db 000001 = -56db (? 1db steps) 111001 = 0db (? 1db steps) 111110 = +5db 111111 = +6db register 39h analogue out1 left
WM8903 production data w pd, rev 4.5, june 2012 154 register address bit label default description r58 (3ah) analogue out1 right 8 hpr_mute 0 right headphone output mute 0 = un-mute 1 = mute 7 hpoutvu 0 headphone output volume update writing a 1 to this bit will update hpoutl and hpoutr volumes simultaneously. (write-only register) 6 hpoutrzc 0 right headphone output zero cross enable 0 = disabled 1 = enabled 5:0 hpoutr_vol [5:0] 10_1101 right headphone output volume 000000 = -57db 000001 = -56db (? 1db steps) 111001 = 0db (? 1db steps) 111110 = +5db 111111 = +6db register 3ah analogue out1 right register address bit label default description r59 (3bh) analogue out2 left 8 lineoutl_mute 0 left line output mute 0 = un-mute 1 = mute 7 lineoutvu 0 line output volume update writing a 1 to this bit will update lineoutl and lineoutr volumes simultaneously. (write-only register) 6 lineoutlzc 0 left line output zero cross enable 0 = disabled 1 = enabled 5:0 lineoutl_vol [5:0] 11_1001 left line output volume 000000 = -57db 000001 = -56db (? 1db steps) 111001 = 0db (? 1db steps) 111110 = +5db 111111 = +6db register 3bh analogue out2 left
production data WM8903 w pd, rev 4.5, june 2012 155 register address bit label default description r60 (3ch) analogue out2 right 8 lineoutr_mute 0 right line output mute 0 = un-mute 1 = mute 7 lineoutvu 0 line output volume update writing a 1 to this bit will update lineoutl and lineoutr volumes simultaneously. (write-only register) 6 lineoutrzc 0 right line output zero cross enable 0 = disabled 1 = enabled 5:0 lineoutr_vol [5:0] 11_1001 right line output volume 000000 = -57db 000001 = -56db (? 1db steps) 111001 = 0db (? 1db steps) 111110 = +5db 111111 = +6db register 3ch analogue out2 right register address bit label default description r62 (3eh) analogue out3 left 8 spkl_mute 1 left speaker output mute 0 = un-mute 1 = mute 7 spkvu 0 speaker output volume update writing a 1 to this bit will update lon/lop and ron/rop volumes simultaneously. (write-only register) 6 spklzc 0 left speaker output zero cross enable 0 = disabled 1 = enabled 5:0 spkl_vol [5:0] 11_1001 left speaker output volume 000000 = -57db 000001 = -56db (? 1db steps) 111001 = 0db (? 1db steps) 111110 = +5db 111111 = +6db register 3eh analogue out3 left
WM8903 production data w pd, rev 4.5, june 2012 156 register address bit label default description r63 (3fh) analogue out3 right 8 spkr_mute 1 right speaker output mute 0 = un-mute 1 = mute 7 spkvu 0 speaker output volume update writing a 1 to this bit will update lon/lop and ron/rop volumes simultaneously. (write-only register) 6 spkrzc 0 right speaker output zero cross enable 0 = disabled 1 = enabled 5:0 spkr_vol [5:0] 11_1001 right speaker output volume 000000 = -57db 000001 = -56db (? 1db steps) 111001 = 0db (? 1db steps) 111110 = +5db 111111 = +6db register 3fh analogue out3 right register address bit label default description r65 (41h) analogue spk output control 0 1 spk_discharge 0 speaker discharge enable 0 = disabled 1 = enable 0 vroi 0 select vmid_tie_ena resistance for disabled differential lineouts 0 = 20k ohm 1 = 500 ohm register 41h analogue spk output control 0 register address bit label default description r67 (43h) dc servo 0 4 dcs_master_ena 1 dc servo master control 0 = dc servo reset 1 = dc servo enabled 3:0 dcs_ena [3:0] 0000 dc servo enable [3] - hpoutl enable [2] - hpoutr enable [1] - lineoutl enable [0] - lineoutr enable register 43h dc servo 0
production data WM8903 w pd, rev 4.5, june 2012 157 register address bit label default description r69 (45h) dc servo 2 1:0 dcs_mode [1:0] 00 dc servo mode 00 = write_stop 01 = write_update 10 = start_stop 11 = start_update register 45h dc servo 2 register address bit label default description r71 (47h) dc servo 4 7:0 dcs_hpoutl_write_val [7:0] 0000_0000 value to send to left headphone output servo in a write mode two?s complement format. lsb is 0.25mv. range is +/-32mv register 47h dc servo 4 register address bit label default description r72 (48h) dc servo 5 7:0 dcs_hpoutr_write_val [7:0] 0000_0000 value to send to right headphone output servo in a write mode two?s complement format. lsb is 0.25mv. range is +/-32mv register 48h dc servo 5 register address bit label default description r73 (49h) dc servo 6 7:0 dcs_loutl_write_val [7:0] 0000_0000 value to send to left line output servo in a write mode two?s complement format. lsb is 0.25mv. range is +/-32mv register 49h dc servo 6 register address bit label default description r74 (4ah) dc servo 7 7:0 dcs_loutr_write_val [7:0] 0000_0000 value to send to right line output servo in a write mode two?s complement format. lsb is 0.25mv. range is +/-32mv register 4ah dc servo 7
WM8903 production data w pd, rev 4.5, june 2012 158 register address bit label default description r81 (51h) dc servo readback 1 7:0 dcs_hpoutl_integ [7:0] 0000_0000 readback value on left headphone output servo. two?s complement format. lsb is 0.25mv. range is +/-32mv (read-only register) register 51h dc servo readback 1 register address bit label default description r82 (52h) dc servo readback 2 7:0 dcs_hpoutr_integ [7:0] 0000_0000 readback value on right headphone output servo. two?s complement format. lsb is 0.25mv. range is +/-32mv (read-only register) register 52h dc servo readback 2 register address bit label default description r83 (53h) dc servo readback 3 7:0 dcs_loutl_integ [7:0] 0000_0000 readback value on left line output servo. two?s complement format. lsb is 0.25mv. range is +/-32mv (read-only register) register 53h dc servo readback 3 register address bit label default description r84 (54h) dc servo readback 4 7:0 dcs_loutr_integ [7:0] 0000_0000 readback value on right line output servo. two?s complement format. lsb is 0.25mv. range is +/-32mv (read-only register) register 54h dc servo readback 4 register address bit label default description r90 (5ah) analogue hp 0 7 hpl_rmv_short 0 removes hpl short 0 = hpl short enabled 1 = hpl short removed for normal operation, this bit should be set as the final step of the hpl enable sequence. 6 hpl_ena_outp 0 enables hpl output stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the dc offset cancellation has been scheduled.
production data WM8903 w pd, rev 4.5, june 2012 159 register address bit label default description 5 hpl_ena_dly 0 enables hpl intermediate stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the output signal path has been configured, and before dc offset cancellation is scheduled. this bit should be set with at least 20us delay after hpl_ena. 4 hpl_ena 0 enables hpl input stage 0 = disabled 1 = enabled for normal operation, this bit should be set as the first step of the hpl enable sequence. 3 hpr_rmv_short 0 removes hpr short 0 = hpr short enabled 1 = hpr short removed for normal operation, this bit should be set as the final step of the hpr enable sequence. 2 hpr_ena_outp 0 enables hpr output stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the dc offset cancellation has been scheduled. 1 hpr_ena_dly 0 enables hpr intermediate stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the output signal path has been configured, and before dc offset cancellation is scheduled. this bit should be set with at least 20us delay after hpr_ena. 0 hpr_ena 0 enables hpr input stage 0 = disabled 1 = enabled for normal operation, this bit should be set as the first step of the hpr enable sequence. register 5ah analogue hp 0 register address bit label default description r94 (5eh) analogue lineout 0 7 lineoutl_rmv_short 0 removes lineoutl short 0 = lineoutl short enabled 1 = lineoutl short removed for normal operation, this bit should be set as the final step of the lineoutl enable sequence. 6 lineoutl_ena_outp 0 enables lineoutl output stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the dc offset cancellation has been scheduled.
WM8903 production data w pd, rev 4.5, june 2012 160 register address bit label default description 5 lineoutl_ena_dly 0 enables lineoutl intermediate stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the output signal path has been configured, and before dc offset cancellation is scheduled. this bit should be set with at least 20us delay after lineoutl_ena. 4 lineoutl_ena 0 enables lineoutl input stage 0 = disabled 1 = enabled for normal operation, this bit should be set as the first step of the lineoutl enable sequence. 3 lineoutr_rmv_short 0 removes lineoutr short 0 = lineoutr short enabled 1 = lineoutr short removed for normal operation, this bit should be set as the final step of the lineoutr enable sequence. 2 lineoutr_ena_outp 0 enables lineoutr output stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the dc offset cancellation has been scheduled. 1 lineoutr_ena_dly 0 enables lineoutr intermediate stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the output signal path has been configured, and before dc offset cancellation is scheduled. this bit should be set with at least 20us delay after lineoutr_ena. 0 lineoutr_ena 0 enables lineoutr input stage 0 = disabled 1 = enabled for normal operation, this bit should be set as the first step of the lineoutr enable sequence. register 5eh analogue lineout 0 register address bit label default description r98 (62h) charge pump 0 0 cp_ena 0 enable charge-pump digits 0 = disable 1 = enable register 62h charge pump 0
production data WM8903 w pd, rev 4.5, june 2012 161 register address bit label default description r104 (68h) class w 0 0 cp_dyn_pwr 0 enable dynamic charge pump power control 0 = charge pump controlled by volume register settings 1 = charge pump controlled by real-time audio level register 68h class w 0 register address bit label default description r108 (6ch) write sequencer 0 8 wsmd_clk_ena 0 write sequencer / mic detect clock enable. 0 = disabled 1 = enabled 4:0 wseq_write_index [4:0] 0_0000 sequence write index. this is the memory location to which any updates to r109 and r110 will be copied. 0 to 31 = ram addresses register 6ch write sequencer 0 register address bit label default description r109 (6dh) write sequencer 1 14:12 wseq_data_width [2:0] 000 width of the data block written in this sequence step. 000 = 1 bit 001 = 2 bits 010 = 3 bits 011 = 4 bits 100 = 5 bits 101 = 6 bits 110 = 7 bits 111 = 8 bits 11:8 wseq_data_start [3:0] 0000 bit position of the lsb of the data block written in this sequence step. 0000 = bit 0 ? 1111 = bit 15 7:0 wseq_addr [7:0] 0000_0000 control register address to be written to in this sequence step. register 6dh write sequencer 1 register address bit label default description r110 (6eh) write sequencer 2 14 wseq_eos 0 end of sequence flag. this bit indicates whether the control write sequencer should stop after executing this step. 0 = not end of sequence 1 = end of sequence (stop the sequencer after this step). 11:8 wseq_delay [3:0] 0000 time delay after executing this step. total delay time per st ep (including execution)= 62.5s (2^wseq_delay + 8)
WM8903 production data w pd, rev 4.5, june 2012 162 register address bit label default description 7:0 wseq_data [7:0] 0000_0000 data to be written in this sequence step. when the data width is less than 8 bits, then one or more of the msbs of wseq_data are ignored. it is recommended that unused bits be set to 0. register 6eh write sequencer 2 register address bit label default description r111 (6fh) write sequencer 3 9 wseq_abort 0 writing a 1 to this bit aborts the current sequence and returns control of the device back to the serial control interface. (write-only register) 8 wseq_start 0 writing a 1 to this bit starts the write sequencer at the memory location indicated by the wseq_start_index field. the sequence continues until it reaches an ?end of sequence? flag. at the end of the sequence, this bit will be reset by the write sequencer. (write-only register) 5:0 wseq_start_index [5:0] 00_0000 sequence start index. this is the memory location of the first command in the selected sequence. 0 to 31 = ram addresses 32 to 48 = rom addresses 49 to 63 = reserved register 6fh write sequencer 3 register address bit label default description r112 (70h) write sequencer 4 9:4 wseq_current_index [5:0] 00_0000 sequence current index. this is the location of the most recently accessed command in the write sequencer memory. (read-only register) 0 wseq_busy 0 sequencer busy flag 0 = sequencer idle 1 = sequencer busy note: it is not possible to write to control registers via the control interface while the sequencer is busy. (read-only register) register 70h write sequencer 4
production data WM8903 w pd, rev 4.5, june 2012 163 register address bit label default description r116 (74h) gpio control 1 13:8 gp1_fn [5:0] 00_0000 gpio 1 pin function select 00h = gpio output 01h = reserved 02h = irq output 03h = gpio input 04h = micbias current detect 05h = micbias short circuit detect 06h = dmic_lr clock output 07h = reserved 08h = fll lock output 09h = fll clock output 0ah to 3fh = reserved 7 gp1_dir 1 gpio pin direction 0 = output 1 = input 6 gp1_op_cfg 0 output pin configuration 0 = cmos 1 = open-drain 5 gp1_ip_cfg 1 input pin configuration 0 = active low 1 = active high 4 gp1_lvl 0 gpio output level (when gp1_fn = 00000) 0 = logic 0 1 = logic 1 3 gp1_pd 1 gpio pull-down enable 0 = pull-down disabled 1 = pull-down enabled (approx 100k ? ) 2 gp1_pu 0 gpio pull-up enable 0 = pull-up disabled 1 = pull-up enabled (approx 100k ? ) 1 gp1_intmode 0 gpio interrupt mode 0 = level triggered 1 = edge triggered 0 gp1_db 0 gpio de-bounce 0 = gpio is not debounced 1 = gpio is debounced register 74h gpio control 1 register address bit label default description r117 (75h) gpio control 2 13:8 gp2_fn [5:0] 00_0000 gpio 2 pin function select 00h = gpio output 01h = reserved 02h = irq output 03h = gpio input 04h = micbias current detect 05h = micbias short circuit detect 06h = dmic_dat data input 07h = reserved 08h = fll lock output 09h = fll clock output
WM8903 production data w pd, rev 4.5, june 2012 164 register address bit label default description 0ah to 3fh = reserved 7 gp2_dir 1 gpio pin direction 0 = output 1 = input 6 gp2_op_cfg 0 output pin configuration 0 = cmos 1 = open-drain 5 gp2_ip_cfg 1 input pin configuration 0 = active low 1 = active high 4 gp2_lvl 0 gpio output level (when gp2_fn = 00000) 0 = logic 0 1 = logic 1 3 gp2_pd 1 gpio pull-down enable 0 = pull-down disabled 1 = pull-down enabled (approx 100k ? ) 2 gp2_pu 0 gpio pull-up enable 0 = pull-up disabled 1 = pull-up enabled (approx 100k ? ) 1 gp2_intmode 0 gpio interrupt mode 0 = level triggered 1 = edge triggered 0 gp2_db 0 gpio de-bounce 0 = gpio is not debounced 1 = gpio is debounced register 75h gpio control 2 register address bit label default description r118 (76h) gpio control 3 13:8 gp3_fn [5:0] 00_0000 gpio 3 pin function select 00h = gpio output 01h = reserved 02h = irq output 03h = gpio input 04h = micbias current detect 05h = micbias short circuit detect 06h = reserved 07h = reserved 08h = fll lock output 09h = fll clock output 0ah to 3fh = reserved 7 gp3_dir 1 gpio pin direction 0 = output 1 = input 6 gp3_op_cfg 0 output pin configuration 0 = cmos 1 = open-drain 5 gp3_ip_cfg 1 input pin configuration 0 = active low 1 = active high
production data WM8903 w pd, rev 4.5, june 2012 165 register address bit label default description 4 gp3_lvl 0 gpio output level (when gp3_fn = 00000) 0 = logic 0 1 = logic 1 3 gp3_pd 1 gpio pull-down enable 0 = pull-down disabled 1 = pull-down enabled (approx 100k ? ) 2 gp3_pu 0 gpio pull-up enable 0 = pull-up disabled 1 = pull-up enabled (approx 100k ? ) 1 gp3_intmode 0 gpio interrupt mode 0 = level triggered 1 = edge triggered 0 gp3_db 0 gpio de-bounce 0 = gpio is not debounced 1 = gpio is debounced register 76h gpio control 3 register address bit label default description r119 (77h) gpio control 4 13:8 gp4_fn [5:0] 00_0010 gpio 4 pin function select 00h = gpio output 01h = reserved 02h = irq output 03h = gpio input 04h = micbias current detect 05h = micbias short circuit detect 06h = reserved 07h = reserved 08h = fll lock output 09h = fll clock output 0ah to 3fh = reserved 7 gp4_dir 0 gpio pin direction 0 = output 1 = input 6 gp4_op_cfg 0 output pin configuration 0 = cmos 1 = open-drain 5 gp4_ip_cfg 1 input pin configuration 0 = active low 1 = active high 4 gp4_lvl 0 gpio output level (when gp4_fn = 00000) 0 = logic 0 1 = logic 1 3 gp4_pd 0 gpio pull-down enable 0 = pull-down disabled 1 = pull-down enabled (approx 100k ? ) 2 gp4_pu 0 gpio pull-up enable 0 = pull-up disabled 1 = pull-up enabled (approx 100k ? )
WM8903 production data w pd, rev 4.5, june 2012 166 register address bit label default description 1 gp4_intmode 0 gpio interrupt mode 0 = level triggered 1 = edge triggered 0 gp4_db 0 gpio de-bounce 0 = gpio is not debounced 1 = gpio is debounced register 77h gpio control 4 register address bit label default description r120 (78h) gpio control 5 13:8 gp5_fn [5:0] 00_0001 gpio 5 pin function select 00h = gpio output 01h = bclk 02h = irq output 03h = gpio input 04h = micbias current detect 05h = micbias short circuit detect 06h = reserved 07h = reserved 08h = fll lock output 09h = fll clock output 0ah to 3fh = reserved 7 gp5_dir 1 gpio pin direction 0 = output 1 = input 6 gp5_op_cfg 0 output pin configuration 0 = cmos 1 = open-drain 5 gp5_ip_cfg 1 input pin configuration 0 = active low 1 = active high 4 gp5_lvl 0 gpio output level (when gp5_fn = 00000) 0 = logic 0 1 = logic 1 3 gp5_pd 0 gpio pull-down enable 0 = pull-down disabled 1 = pull-down enabled (approx 100k ? ) 2 gp5_pu 0 gpio pull-up enable 0 = pull-up disabled 1 = pull-up enabled (approx 100k ? ) 1 gp5_intmode 0 gpio interrupt mode 0 = level triggered 1 = edge triggered 0 gp5_db 0 gpio de-bounce 0 = gpio is not debounced 1 = gpio is debounced register 78h gpio control 5
production data WM8903 w pd, rev 4.5, june 2012 167 register address bit label default description r121 (79h) interrupt status 1 15 micshrt_eint 0 micbias short circuit detect irq status 0 = short circuit current irq not set 1 = short circuit current irq set (read-only register) 14 micdet_eint 0 micbias current detect irq status 0 = current detect irq not set 1 = current detect irq set (read-only register) 13 wseq_busy_eint 0 write sequencer busy irq status 0 = wseq irq not set 1 = wseq irq set the write sequencer asserts this flag when it has completed a programmed sequence - ie it indicates that the write sequencer is not busy. (read-only register) 5 fll_lock_eint 0 fll lock irq status 0 = fll lock irq not set 1 = fll lock irq set (read-only register) 4 gp5_eint 0 gpio5 irq status 0 = gpio5 irq not set 1 = gpio5 irq set (read-only register) 3 gp4_eint 0 gpio4 irq status 0 = gpio4 irq not set 1 = gpio4 irq set (read-only register) 2 gp3_eint 0 gpio3/addr irq status 0 = gpio3 irq not set 1 = gpio3 irq set (read-only register) 1 gp2_eint 0 gpio2/dmic_dat irq status 0 = gpio2 irq not set 1 = gpio2 irq set (read-only register) 0 gp1_eint 0 gpio1/dmic_lr irq status 0 = gpio1 irq not set 1 = gpio1 irq set (read-only register) register 79h interrupt status 1 register address bit label default description r122 (7ah) interrupt status 1 mask 15 im_micshrt_eint 1 interrupt mask for mic short circuit detect 0 = not masked 1 = masked 14 im_micdet_eint 1 interrupt mask for mic current detect 0 = not masked 1 = masked
WM8903 production data w pd, rev 4.5, june 2012 168 register address bit label default description 13 im_wseq_busy_eint 1 interrupt mask for wseq busy indication 0 = not masked 1 = masked 5 im_fll_lock_eint 1 interrupt mask for fll lock 0 = not masked 1 = masked 4 im_gp5_eint 1 interrupt mask for gpio5 0 = not masked 1 = masked 3 im_gp4_eint 1 interrupt mask for gpio4 0 = not masked 1 = masked 2 im_gp3_eint 1 interrupt mask for gpio3/addr 0 = not masked 1 = masked 1 im_gp2_eint 1 interrupt mask for gpio2/dmic_dat 0 = not masked 1 = masked 0 im_gp1_eint 1 interrupt mask for gpio1/dmic_lr 0 = not masked 1 = masked register 7ah interrupt status 1 mask register address bit label default description r123 (7bh) interrupt polarity 1 15 micshrt_inv 0 micbias short circuit detect polarity 0 = detect current increase above threshold 1 = detect current decrease below threshold 14 micdet_inv 0 micbias current detect polarity 0 = detect current increase above threshold 1 = detect current decrease below threshold 5 fll_lock_inv 0 fll lock polarity 0 = non-inverted 1 = inverted register 7bh interrupt polarity 1 register address bit label default description r126 (7eh) interrupt control 0 irq_pol 0 interrupt output polarity 0 = active high 1 = active low register 7eh interrupt control
production data WM8903 w pd, rev 4.5, june 2012 169 register address bit label default description r128 (80h) fll control 1 7:4 fll_gain [3:0] 0000 gain applied to error 0000 = x 1 (recommended value) 0001 = x 2 0010 = x 4 0011 = x 8 0100 = x 16 0101 = x 32 0110 = x 64 0111 = x 128 1000 = x 256 recommended that this register is not changed from default. 3 fll_hold 0 fll hold select 0 = disabled 1 = enabled this feature enables free-running mode in fll when reference clock is removed 2 fll_frac 0 fractional enable 0 = integer mode 1 = fractional mode fractional mode is recommended in all cases 0 fll_ena 0 fll enable 0 = disabled 1 = enabled register 80h fll control 1 register address bit label default description r129 (81h) fll control 2 12:11 fll_clk_src [1:0] 00 fll clock source 00 = mclk 01 = bclk 10 = lrc 11 = reserved 10:9 fll_clk_ref _div [1:0] 00 fll clock reference divider 00 = mclk / 1 01 = mclk / 2 10 = mclk / 4 11 = mclk / 8 mclk (or other input reference) must be divided down to <=13.5mhz. for lower power operation, the reference clock can be divided down further if desired. 8:6 fll_ctrl_ra te [2:0] 000 frequency of the fll control block 000 = fvco / 1 (recommended value) 001 = fvco / 2 010 = fvco / 3 011 = fvco / 4 100 = fvco / 5
WM8903 production data w pd, rev 4.5, june 2012 170 register address bit label default description 101 = fvco / 6 110 = fvco / 7 111 = fvco / 8 recommended that this register is not changed from default. 5:3 fll_outdiv [2:0] 000 fout clock divider 000 = 2 001 = 4 010 = 8 011 = 16 100 = 32 101 = 64 110 = 128 111 = 256 (fout = fvco / fll_outdiv) 2:0 fll_fratio [2:0] 000 f vco clock divider 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 1xx = divide by 16 000 recommended for f ref > 1mhz 100 recommended for f ref < 64khz register 81h fll control 2 register address bit label default description r130 (82h) fll control 3 15:0 fll_k [15:0] 0000_0000 _0000_000 0 fractional multiply for fref (msb = 0.5) register 82h fll control 3 register address bit label default description r131 (83h) fll control 4 9:0 fll_n [9:0] 00_0000_0 000 integer multiply for fref (lsb = 1) register 83h fll control 4 register address bit label default description r164 (a4h) clock rate test 4 9 adc_dig_mic 0 enables digital microphone mode. 0 = audio dsp input is from adc 1 = audio dsp input is from digital microphone interface register a4h clock rate test 4
production data WM8903 w pd, rev 4.5, june 2012 171 register address bit label default description r172 (ach) analogue output bias 0 6:4 pga_bias [2:0] 000 headphone and lineout pga bias control 000 = normal bias 001 = normal bias x 1.5 010 = normal bias x 0.75 011 = normal bias x 0.5 100 = normal bias x 0.33 101 = normal bias 110 = normal bias 111 = normal bias x 2 register ach analogue output bias 0 register address bit label default description r187 (bbh) analogue output bias 2 2:0 outputs_bias [2:0] 000 headphone and lineout output drivers bias control 000 = normal bias 001 = normal bias x 1.5 010 = normal bias x 0.75 011 = normal bias x 0.5 100 = normal bias x 0.33 101 = normal bias 110 = normal bias 111 = normal bias x 2 register bbh analogue output bias 2
WM8903 production data w pd, rev 4.5, june 2012 172 applications information recommended external components figure 67 recommended external components notes: 1. decoupling capacitors x5r ceramic capacitor is recommended for capacitors c1, c2, c3, c4, c6, c7, c12 and c13. all decoupling capacitors should be positioned as close to the WM8903 as possible. the positioning of c12 and c13 is particularly important - these should be as close to the WM8903 as possible. 2. charge pump capacitors specific recommendations for c5, c6 and c7 are provided in table 85. note that two different recommendations are provided for these components; either of these components is suitable, depending upon size requirements and availability. the positioning of c5 is very important - this should be as close to the WM8903 as possible. it is important to select a suitable capacitor type for the c harge pump. note that the capacitance may vary with dc voltage; care is required to ensure that required capacitance is achieved at t he applicable operating voltage, as specified in table 85. the capacitor datasheet should be c onsulted for this information. component required capacitance value part number voltage type size c5 (cfb1-cfb2) ? 1 ? f at 2vdc 2.2 ? f kemet c0402c225m9pac 6.3v x5r 0402 2.2 ? f murata grm155r60j225me15_eia 6.3v x5r 0402 c6 (vneg) c7 (vpos) ? 2 ? f at 2vdc 2.2 ? f murata grm188r61a225ke34d 10v x5r 0603 4.7 ? f murata grm155r60j475m_eia 6.3v x5r 0402 table 85 charge pump capacitors
production data WM8903 w pd, rev 4.5, june 2012 173 3. zobel networks the zobel network shown in figure 67 is required on hpoutl, hpoutr, lineoutl and lineoutr whenever that output is enabled. stability of these ground-referenced outputs across a ll process corners cannot be guaranteed without the zobel network components. (note that, if any ground-referenced output pin is not required, the zobel network components can be omitted from the output pin, and the pin can be left floating.) the zobel network requirement is detailed further in the applications note wan_0212 ?class w headphone impedance compensation?. zobel networks (cc16, c17, c18, c19, r9, r10, r11, r12) should be positioned r easonably close to the WM8903. 4. microphone grounding r3 and r4 can be populated with other values to re move common mode noise on the microphone if required.
WM8903 production data w pd, rev 4.5, june 2012 174 mic detection sequence using micbias current this section details an example sequence which su mmarises how the host processor can configure and detect the events supported by the micbias cu rrent detect function (see ?electret condenser microphone interface?): ? mic insertion/removal ? hook switch press/release figure 68 shows an example of how the micbias cu rrent flow varies versus time, during mic insertion and hook switch events. the y axis is annotated with the mic detection thresholds, and the x axis is annotated with the stages of an example s equence as detailed in table 86, to illustrate how the host processor can implement mic insertion and hook switch detection. the sequence assumes that the microphone insert ion and hook switch detection functions are monitored by polling the interrupt fl ags using the control interface. no te that the maximum mechanical bounce times for mic insertion and removal must be fully understood by the software programmer. a gpio pin could be used as an al ternative mechanism to monitor the micbias detection functions. this enables the host processor to detect mechanical bounce at any time. figure 68 mic insert and hook switch detect: example micbias current plot
production data WM8903 w pd, rev 4.5, june 2012 175 step details 1 mic not inserted. to detect mic insertion, host processor must initialise interrupts and clear micdet_inv = 0. at every step, the host processor should poll the interrupt status register. 2 mechanical bounce of jack socket during mic insertion. host processor may already detect a mic insertion interrupt (micdet_eint) during this step. once detected, the hos t processor can set micdet_inv = 1, unless mechanical bounce can last longer than the shortest possible t det , in which case the host processor should not set micdet_inv = 1 until step 3. 3 mic fully inserted. if not already set, the host processor must now set micdet_inv = 1. to detect hook switch press, the host processor must clear micshrt_inv = 0. at this step, the diagram shows no ac current swing, due to a very low ambient noise level. 4 mic fully inserted. diagram shows ac current swing due to high levels of background noise (such as wind). 5 mechanical bounce during hook switch press. the hook switch in terrupt is unlikely to be set during this step, because 10 successive samples of the micbias current exceeding t he hook switch threshold have not yet been sampled. 6 hook switch is fully pressed down. after t short , 10 successive samples of the micbias current exceeding the hook switch threshold have been detected, hence a hook switch interrupt (micshrt_eint) will be generated, and the host processor can immediately set micshrt_inv = 1. 7 mechanical bounce during hook switch release. the hook switch interrupt is unlikely to be set during this step, because 10 successive samples of the micbias current lower than the hook switch threshold have not yet been sampled. 8 hook switch fully released. after t short , 10 successive samples of the micbias current lower than the hook switch threshold have been detected, hence a hook switch interrupt (micshrt_eint) will be generated, and the host processor can immediately clear micshrt_inv = 0. 9 mechanical bounce of jack socket during mic removal. host processor may already detect a mic removal interrupt (micdet_eint) during this step. once detected, the hos t processor can clear micdet_inv = 0, unless mechanical bounce can last longer than the shortest possible t det , in which case the host processor should not clear micdet_inv = 0 until step 10. 10 mic fully removed. if not already cleared, the host processor must now clear micdet_inv = 0. table 86 mic insert and hook switch detect: example sequence alternatively, utilising a gpio pin to monitor the micbias current detect functionality permits the host processor to monitor the steady state of mi crophone detection or hook switch press functions. because the gpio shows the steady state conditi on, software de-bounce may be easier to implement in the host processor, dependant on the processor performance characterist ics, hence use of the gpio is likely to simplify the rejection of mec hanical bounce. changes of state in the gpio pin are also subject to the time delays t det and t short . further details can be found in the applicati ons note wan_0213 ?WM8903 ecm mic detection using micbias current?.
WM8903 production data w pd, rev 4.5, june 2012 176 package dimensions notes: 1. dimension b applied to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 2. falls within jedec, mo-220. 3. all dimensions are in millimetres 4. this drawing is subject to change without notice. 5. refer to applications note wan_0118 for further information. dm110.a fl: 40 pin qfn plastic package 5 x 5 x 0.55 mm body, 0.40 mm lead pitch c aaa index area (d/2 x e/2) c aaa 2 x 2 x top view d e c 0.08 c ccc a a1 c (a3) seating plane 1 18 17 40 x b 21 40 x l d2 e2 see detail a b c bbb m a b b a a 39 40 1 2 10 11 30 31 e detail a terminal tip r datum e e/2 1 symbols dimensions (mm) min nom max note a a1 a3 b d d2 e e2 e l 0.50 0.55 0.60 0.05 0.035 0 0.152 ref 0.25 0.20 0.15 5.00 bsc 3.50 3.40 3.30 5.00 bsc 0.4 bsc 3.40 3.50 3.30 0.35 0.4 0.45 1 2 2 aaa bbb ccc ref: 0.10 0.10 0.10 jedec, mo-220 ? whhe-1 tolerances of form and position s r0.2 (pin #1 id) exposed gnd paddle 6 b c ddd a b c ddd a s 1.15 1.25 1.35 ddd 0.10
production data WM8903 w pd, rev 4.5, june 2012 177 important notice wolfson microelectronics plc (?wol fson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specifications in effect at t he date of shipment. wolfson reserves the right to make changes to its products and s pecifications or to discontinue any produc t or service without notice. customers should therefore obtain the latest version of relevant informati on from wolfson to verify that the information is current. testing and other quality control techniques are utilised to the extent wolfson deems necessary to support its warranty. specific testing of all parameters of each device is not necessarily performed unless requi red by law or regulation. in order to minimise risks associated with customer app lications, the customer must use adequate design and operating safeguards to minimise inherent or proc edural hazards. wolfson is not liable fo r applications assistance or customer product design. the customer is solely responsible for its se lection and use of wolfson products . wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to re sult in personal injury, death or severe property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of wolfson covering or relating to any combination, machine, or pr ocess in which its products or services might be or are used. any prov ision or publication of any third party?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective third party owner. reproduction of information from wolfson datasheets is per missible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other not ices (including this notice) and conditions. wolfson is not liable for any unauthorised alteration of such in formation or for any reliance placed thereon. any representations made, warranties giv en, and/or liabilities accepted by any pers on which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. address wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com
WM8903 production data w pd, rev 4.5, june 2012 178 revision history date rev originator changes 21/07/11 4.1 ss correction to audio interface, slave mode specifications. ?dacdat set-up time to bclk rising edge? specif ication changed to 20ns minimum. 08/08/11 4.2 ph all read-only and write-only registers are specifically identified as read- only or write-only respectively. 28/09/11 4.3 ph lin_vol and rin_vol registers updated; 00000 = -1.55db 01/03/12 4.4 jmacd order codes updated from WM8903lgefk/v and WM8903lgefk/rv to WM8903 c lgefk and WM8903 c lgefk/r to reflect change to copper wire bonding 01/03/12 4.4 jmacd msl level changed from msl3 to msl1 01/03/12 4.4 jmacd package diagram changed to dm110.a 14/06/12 4.5 ss correction to audio interface, sl ave mode specifications. ?adcdat propagation delay from bclk falling edge? specification changed to 30ns maximum.

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